URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] [ion/] [trunk/] [tools/] [slite/] [src/] - Rev 61

Rev	Log message	Author	Age	Path
61	SW simulator updated: new mips-1 memory map and trap addresses slightly better command line argument parsing	ja_rd	4897d 01h	/ion/trunk/tools/slite/src/
53	SW simulator: Major change in logging code. Changes are logged now with the address of the instruction that caused them. These changes make the HW simulation TB's life easier.	ja_rd	4899d 06h	/ion/trunk/tools/slite/src/
44	slite: cleaned up memory allocation/deallocation code	ja_rd	4901d 10h	/ion/trunk/tools/slite/src/
32	slite: catch 1-instruction endless loops now can run unattended; will stop at the end of main()	ja_rd	4903d 11h	/ion/trunk/tools/slite/src/
31	Major refactor in slite: supports memory map with more than 1 block indentation made homogeneous unused code removed	ja_rd	4903d 11h	/ion/trunk/tools/slite/src/
27	SW simulator updated: now supports CP0 cause register and traps in delay slots	ja_rd	4905d 09h	/ion/trunk/tools/slite/src/
16	SW simulator now shows HI and LO in status	ja_rd	4906d 23h	/ion/trunk/tools/slite/src/
11	SW signed multiplication simulation now lets compiler do the 64-bit arithmetic	ja_rd	4907d 11h	/ion/trunk/tools/slite/src/
7	Traps are now simulated as per MIPS specifications: EPC point to victim instruction (break/syscall)	ja_rd	4908d 01h	/ion/trunk/tools/slite/src/
5	SW simulator now logs failed assertions instead of quitting	ja_rd	4908d 03h	/ion/trunk/tools/slite/src/
2	First commit (includes 'hello' demo)	ja_rd	4908d 13h	/ion/trunk/tools/slite/src/