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[/] [ion/] [trunk/] [vhdl/] - Rev 101

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Rev	Log message	Author	Age	Path
101	FIX: code_rd_vma asserted only after reset is done ADDED cache control bits to CP0 status register ADDED cache control outputs	ja_rd	4845d 05h	/ion/trunk/vhdl/
98	CPU rd and wr data address buses unified	ja_rd	4869d 15h	/ion/trunk/vhdl/
96	CPU rd and wr data address buses unified	ja_rd	4869d 15h	/ion/trunk/vhdl/
95	BUG FIX: cache stub properly handles all kind of cycles now	ja_rd	4880d 11h	/ion/trunk/vhdl/
94	Pregenerated demo 'hello' files updated	ja_rd	4880d 11h	/ion/trunk/vhdl/
85	BUG FIX: log2 function was wrong	ja_rd	4880d 11h	/ion/trunk/vhdl/
84	Added 'trigger address' for file logging to both the vhdl TB and the python script	ja_rd	4880d 11h	/ion/trunk/vhdl/
83	BUG FIX: LHU was not doing sign extension properly BUG FIX: SLTIU decoding was wrong	ja_rd	4880d 11h	/ion/trunk/vhdl/
82	bug fix: SLTI wasn't working properly in some cases	ja_rd	4882d 12h	/ion/trunk/vhdl/
81	Added a wait state to the SRAM area for the DE-1 demo code	ja_rd	4889d 06h	/ion/trunk/vhdl/
80	Stub cache fixed Now supports code refills from static 16- and 8- bit memory Plus many mirror corrections	ja_rd	4889d 06h	/ion/trunk/vhdl/
76	Adapted pregenerated vhdl files to latest changes	ja_rd	4890d 09h	/ion/trunk/vhdl/
75	Added support for 8-bit-wide static memory (e.g. Flash) Updated demo 'top' file to use the DE-1 onboard flash	ja_rd	4890d 09h	/ion/trunk/vhdl/
74	Fixed (harmless) error in simulation template 2	ja_rd	4890d 13h	/ion/trunk/vhdl/
73	Fixed comment about write cycles in cache module	ja_rd	4890d 13h	/ion/trunk/vhdl/
72	Fixed stupid bug in SRAM write cycles (setup time violated) Wait states implemented for SRAM wait and read cycles	ja_rd	4890d 13h	/ion/trunk/vhdl/
68	Updated pre-generated vhdl files	ja_rd	4891d 01h	/ion/trunk/vhdl/
64	Refactored memory decoding logic (wait states and read-only attributes unimplemented yet)	ja_rd	4891d 01h	/ion/trunk/vhdl/
63	DE-1 demo top module: added registers for SD interface, switches and 7-seg display	ja_rd	4891d 01h	/ion/trunk/vhdl/
62	CPU fixed: fixed bug in EPC load logic relative to mem_wait stalls parametrized reset and trap vector addresses	ja_rd	4891d 01h	/ion/trunk/vhdl/

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[/] [ion/] [trunk/] [vhdl/] - Rev 101

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