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[/] [ion/] [trunk/] [vhdl/] - Rev 115

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Rev Log message Author Age Path
115 Updated Altera CSV file (pin location file) for DE-1 board
(Added 27MHz clock input)		 ja_rd 4977d 23h /ion/trunk/vhdl/
114 ADDED: 1st version of real cache ja_rd 4978d 00h /ion/trunk/vhdl/
112 Updated simulation package for compatibility to new cache ja_rd 4978d 01h /ion/trunk/vhdl/
103 ADDED cache control inputs (unused) to dummy cache ja_rd 4986d 15h /ion/trunk/vhdl/
101 FIX: code_rd_vma asserted only after reset is done
ADDED cache control bits to CP0 status register
ADDED cache control outputs		 ja_rd 4986d 15h /ion/trunk/vhdl/
98 CPU rd and wr data address buses unified ja_rd 5011d 01h /ion/trunk/vhdl/
96 CPU rd and wr data address buses unified ja_rd 5011d 01h /ion/trunk/vhdl/
95 BUG FIX: cache stub properly handles all kind of cycles now ja_rd 5021d 21h /ion/trunk/vhdl/
94 Pregenerated demo 'hello' files updated ja_rd 5021d 21h /ion/trunk/vhdl/
85 BUG FIX: log2 function was wrong ja_rd 5021d 21h /ion/trunk/vhdl/
84 Added 'trigger address' for file logging to both the
vhdl TB and the python script		 ja_rd 5021d 21h /ion/trunk/vhdl/
83 BUG FIX: LHU was not doing sign extension properly
BUG FIX: SLTIU decoding was wrong		 ja_rd 5021d 21h /ion/trunk/vhdl/
82 bug fix: SLTI wasn't working properly in some cases ja_rd 5023d 22h /ion/trunk/vhdl/
81 Added a wait state to the SRAM area for the DE-1 demo code ja_rd 5030d 16h /ion/trunk/vhdl/
80 Stub cache fixed
Now supports code refills from static 16- and 8- bit memory
Plus many mirror corrections		 ja_rd 5030d 16h /ion/trunk/vhdl/
76 Adapted pregenerated vhdl files to latest changes ja_rd 5031d 19h /ion/trunk/vhdl/
75 Added support for 8-bit-wide static memory (e.g. Flash)
Updated demo 'top' file to use the DE-1 onboard flash		 ja_rd 5031d 19h /ion/trunk/vhdl/
74 Fixed (harmless) error in simulation template 2 ja_rd 5031d 23h /ion/trunk/vhdl/
73 Fixed comment about write cycles in cache module ja_rd 5031d 23h /ion/trunk/vhdl/
72 Fixed stupid bug in SRAM write cycles (setup time violated)
Wait states implemented for SRAM wait and read cycles		 ja_rd 5031d 23h /ion/trunk/vhdl/

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