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[/] [ion/] [trunk/] [vhdl/] - Rev 129

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Rev Log message Author Age Path
129 updated pregenerated demo ('hello') ja_rd 4792d 10h /ion/trunk/vhdl/
128 updated precompiled simulation testbench ja_rd 4792d 10h /ion/trunk/vhdl/
126 added SDRAM verilog simulation model ja_rd 4792d 10h /ion/trunk/vhdl/
121 CPU code reorganized a bit
No new logic, just a few swapped lines and new comments
ja_rd 4838d 10h /ion/trunk/vhdl/
120 Updated main package with lots of wait states for all areas ja_rd 4847d 12h /ion/trunk/vhdl/
119 Updated pre-generated simulation and synthesis demos ja_rd 4847d 12h /ion/trunk/vhdl/
116 Updated demo 'top' file for DE-1 board
- Added reset button debouncing
- Added template for using different clock input
- Uses clock rate generic
ja_rd 4847d 13h /ion/trunk/vhdl/
115 Updated Altera CSV file (pin location file) for DE-1 board
(Added 27MHz clock input)
ja_rd 4847d 15h /ion/trunk/vhdl/
114 ADDED: 1st version of real cache ja_rd 4847d 16h /ion/trunk/vhdl/
112 Updated simulation package for compatibility to new cache ja_rd 4847d 17h /ion/trunk/vhdl/
103 ADDED cache control inputs (unused) to dummy cache ja_rd 4856d 08h /ion/trunk/vhdl/
101 FIX: code_rd_vma asserted only after reset is done
ADDED cache control bits to CP0 status register
ADDED cache control outputs
ja_rd 4856d 08h /ion/trunk/vhdl/
98 CPU rd and wr data address buses unified ja_rd 4880d 17h /ion/trunk/vhdl/
96 CPU rd and wr data address buses unified ja_rd 4880d 17h /ion/trunk/vhdl/
95 BUG FIX: cache stub properly handles all kind of cycles now ja_rd 4891d 13h /ion/trunk/vhdl/
94 Pregenerated demo 'hello' files updated ja_rd 4891d 13h /ion/trunk/vhdl/
85 BUG FIX: log2 function was wrong ja_rd 4891d 14h /ion/trunk/vhdl/
84 Added 'trigger address' for file logging to both the
vhdl TB and the python script
ja_rd 4891d 14h /ion/trunk/vhdl/
83 BUG FIX: LHU was not doing sign extension properly
BUG FIX: SLTIU decoding was wrong
ja_rd 4891d 14h /ion/trunk/vhdl/
82 bug fix: SLTI wasn't working properly in some cases ja_rd 4893d 14h /ion/trunk/vhdl/

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