URL https://opencores.org/ocsvn/ion/ion/trunk

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[/] [ion/] [trunk/] [vhdl/] - Rev 138

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Rev	Log message	Author	Age	Path
138	updated simulation & synthesis pre-generated entities ('hello' code sample)	ja_rd	4794d 21h	/ion/trunk/vhdl/
136	Added debug output to synthesizable MPU template, and connected debug signals to LEDs	ja_rd	4794d 22h	/ion/trunk/vhdl/
134	Added 'unmapped access' flag to CPU core, meant for debug mostly. Eventually this flag will trigger an interrupt.	ja_rd	4794d 22h	/ion/trunk/vhdl/
133	First draft of the SDRAM controller (Still unused in the code working base)	ja_rd	4797d 19h	/ion/trunk/vhdl/
132	Fixed bug in stall logic (stall for back-to-back SW instructions was wrong)	ja_rd	4797d 19h	/ion/trunk/vhdl/
129	updated pregenerated demo ('hello')	ja_rd	4797d 19h	/ion/trunk/vhdl/
128	updated precompiled simulation testbench	ja_rd	4797d 19h	/ion/trunk/vhdl/
126	added SDRAM verilog simulation model	ja_rd	4797d 20h	/ion/trunk/vhdl/
121	CPU code reorganized a bit No new logic, just a few swapped lines and new comments	ja_rd	4843d 19h	/ion/trunk/vhdl/
120	Updated main package with lots of wait states for all areas	ja_rd	4852d 22h	/ion/trunk/vhdl/
119	Updated pre-generated simulation and synthesis demos	ja_rd	4852d 22h	/ion/trunk/vhdl/
116	Updated demo 'top' file for DE-1 board - Added reset button debouncing - Added template for using different clock input - Uses clock rate generic	ja_rd	4852d 23h	/ion/trunk/vhdl/
115	Updated Altera CSV file (pin location file) for DE-1 board (Added 27MHz clock input)	ja_rd	4853d 01h	/ion/trunk/vhdl/
114	ADDED: 1st version of real cache	ja_rd	4853d 01h	/ion/trunk/vhdl/
112	Updated simulation package for compatibility to new cache	ja_rd	4853d 03h	/ion/trunk/vhdl/
103	ADDED cache control inputs (unused) to dummy cache	ja_rd	4861d 17h	/ion/trunk/vhdl/
101	FIX: code_rd_vma asserted only after reset is done ADDED cache control bits to CP0 status register ADDED cache control outputs	ja_rd	4861d 17h	/ion/trunk/vhdl/
98	CPU rd and wr data address buses unified	ja_rd	4886d 03h	/ion/trunk/vhdl/
96	CPU rd and wr data address buses unified	ja_rd	4886d 03h	/ion/trunk/vhdl/
95	BUG FIX: cache stub properly handles all kind of cycles now	ja_rd	4896d 23h	/ion/trunk/vhdl/

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Subversion Repositories ion

[/] [ion/] [trunk/] [vhdl/] - Rev 138

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