OpenCores
URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] [ion/] [trunk/] [vhdl/] - Rev 200

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
200 CPU interrupt input changed to 8-bit vector
Other modules changed accordingly
Interrupts still missing; this is just preparing the interface
ja_rd 4717d 23h /ion/trunk/vhdl/
194 Removed deprecated files from old TB version ja_rd 4719d 15h /ion/trunk/vhdl/
193 Major test bench reorganization:
1.- TB now uses same object code as synthesizable demo.
2.- TB now simulates full MPU system.
3.- Console logging moved to TB package.
4.- Code sample makefiles and modelsim script updated accordingly.
ja_rd 4719d 15h /ion/trunk/vhdl/
191 Separated object code stuff from mcu entity
Object code related stuff now lives in separate file
Makefiles for code samples updated accordingly
Old mcu template deprecated but still in place
ja_rd 4724d 01h /ion/trunk/vhdl/
188 updated hello demo mpu file ja_rd 4732d 17h /ion/trunk/vhdl/
171 CPU bug fix: MFC0 instructions aborted by privilege trap should not modify any register ja_rd 4763d 09h /ion/trunk/vhdl/
162 Fixed stupid mistake in headers (date of project) ja_rd 4769d 22h /ion/trunk/vhdl/
161 Added GPL license info to the vhdl headers
This project is becoming respectable :)
ja_rd 4769d 22h /ion/trunk/vhdl/
159 bug detected but not fixed in cpu
(1st instruction after entering user mode is executed in kernel mode)
ja_rd 4771d 06h /ion/trunk/vhdl/
158 removed file from TB directory which was committed by mistake ja_rd 4771d 07h /ion/trunk/vhdl/
157 Bug fix in the missing coprocesor exception.
The CPU was triggering a privilege exception for the mtc0 that went into user mode.
Logging HDL updated
ja_rd 4772d 16h /ion/trunk/vhdl/
153 Added R3000 compatible support for kernel/user state:
- Implemented KU/IE plus KUp/IEp and KUo/IEo status bits
- Updated startup and test code to account for changes
- Implemented bit DID NOT TEST rfe instruction (not used in code)
- Access to CP0 in user mode triggers 'CpU' trap
- Updated software simulator

Besides, the logging of HI/LO register changes has been temporarily disabled, there's an unfixed bug in it.
ja_rd 4773d 02h /ion/trunk/vhdl/
152 Added R3000 compatible support for kernel/user state:
- Implemented KU/IE plus KUp/IEp and KUo/IEo status bits
- Updated startup and test code to account for changes
- Implemented bit DID NOT TEST rfe instruction (not used in code)
- Access to CP0 in user mode triggers 'CpU' trap
- Updated software simulator

Besides, the logging of HI/LO register changes has been temporarily disabled, there's an unfixed bug in it.
ja_rd 4773d 02h /ion/trunk/vhdl/
151 BUG FIX: major bugs fixed in cache module
1.- sram address was wrong (leftover from previous version)
2.- writes to unmapped areas were blocking the cache
3.- Sequence SW,LW produced a RAW data hazard in some cases
ja_rd 4773d 02h /ion/trunk/vhdl/
145 MAJOR UPDATE: first version of D-Cache ja_rd 4775d 16h /ion/trunk/vhdl/
141 BUG FIX in cache: cpu stall logic was missing key case
2nd SW in a (cached) row was not being stalled
ja_rd 4777d 06h /ion/trunk/vhdl/
140 BUG FIX in cpu: MTCx was using Rs as source instead of Rt
BUG FIX in cpu: cached sequences of S* were failing, byte_we logic was wrong
ja_rd 4777d 06h /ion/trunk/vhdl/
139 updated simulation & synthesis pre-generated entities
('hello' code sample)
ja_rd 4777d 23h /ion/trunk/vhdl/
138 updated simulation & synthesis pre-generated entities
('hello' code sample)
ja_rd 4777d 23h /ion/trunk/vhdl/
136 Added debug output to synthesizable MPU template, and connected debug signals to LEDs ja_rd 4778d 00h /ion/trunk/vhdl/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.