OpenCores
URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] [ion/] [trunk/] [vhdl/] - Rev 53

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
48 Temporary fix to memory decoding constants ja_rd 4893d 03h /ion/trunk/vhdl/
47 Pre-generated simulation test benches updated ja_rd 4893d 03h /ion/trunk/vhdl/
46 First version of cache: stub, 1-word cache
Stub cache tested on simulation and HW, just a stub
Adapted CPU stall logic to 1st version of cache
Adapted all other modules for compatibility with cache		 ja_rd 4893d 03h /ion/trunk/vhdl/
43 added comments to dummy 'cache' stub ja_rd 4895d 11h /ion/trunk/vhdl/
42 Added cache stub module, plus related test bench ja_rd 4897d 06h /ion/trunk/vhdl/
40 pre-generated 'hello' demo updated ja_rd 4897d 06h /ion/trunk/vhdl/
37 functions added to package for standard address decoding ja_rd 4897d 07h /ion/trunk/vhdl/
36 pre-generated simulation test bench TB1 updated
for compatibility to other changes		 ja_rd 4897d 07h /ion/trunk/vhdl/
35 CPU mem_wait logic updated to work with cache ja_rd 4897d 07h /ion/trunk/vhdl/
30 Completed decoding of instructions
(to prevent side effects of invalid opcodes)		 ja_rd 4899d 04h /ion/trunk/vhdl/
28 Core updated:
supports CP0 cause register and traps in delay slots
traps abort next instruction in all cases (incl. jumps/L*/S*)		 ja_rd 4899d 05h /ion/trunk/vhdl/
23 Unimplemented instruction are now trapped (barely tested) ja_rd 4899d 10h /ion/trunk/vhdl/
22 FIXED killer bug in instruction decoder for beq & mfc0
Decoding was incomplete and beq was using wrong ALU input		 ja_rd 4900d 07h /ion/trunk/vhdl/
21 Converted multiplier module reset to synchronous ja_rd 4900d 18h /ion/trunk/vhdl/
18 pre-generated simulation test bench 'hello world' adapted to
new mult module		 ja_rd 4900d 20h /ion/trunk/vhdl/
12 Adapted multiplier unit from Plasma ja_rd 4900d 21h /ion/trunk/vhdl/
8 Trap handling now works as in the MIPS specs:
EPC points to victim instruction (break/syscall)		 ja_rd 4901d 22h /ion/trunk/vhdl/
6 Fix: BREAK now aborts load and jump instructions properly ja_rd 4902d 00h /ion/trunk/vhdl/
2 First commit (includes 'hello' demo) ja_rd 4902d 10h /ion/trunk/vhdl/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.