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[/] [ion/] [trunk/] [vhdl/] [demo/] - Rev 116

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Rev Log message Author Age Path
116 Updated demo 'top' file for DE-1 board
- Added reset button debouncing
- Added template for using different clock input
- Uses clock rate generic		 ja_rd 4847d 14h /ion/trunk/vhdl/demo/
115 Updated Altera CSV file (pin location file) for DE-1 board
(Added 27MHz clock input)		 ja_rd 4847d 16h /ion/trunk/vhdl/demo/
98 CPU rd and wr data address buses unified ja_rd 4880d 18h /ion/trunk/vhdl/demo/
94 Pregenerated demo 'hello' files updated ja_rd 4891d 14h /ion/trunk/vhdl/demo/
76 Adapted pregenerated vhdl files to latest changes ja_rd 4901d 12h /ion/trunk/vhdl/demo/
75 Added support for 8-bit-wide static memory (e.g. Flash)
Updated demo 'top' file to use the DE-1 onboard flash		 ja_rd 4901d 12h /ion/trunk/vhdl/demo/
68 Updated pre-generated vhdl files ja_rd 4902d 04h /ion/trunk/vhdl/demo/
63 DE-1 demo top module:
added registers for SD interface, switches and 7-seg display		 ja_rd 4902d 05h /ion/trunk/vhdl/demo/
59 cleaned up top vhdl module of demo
moved reset sync ff chain to top module
updated pre-generated demo file		 ja_rd 4903d 18h /ion/trunk/vhdl/demo/
57 updated precompiled demo:
single 32-bit BROM instead of 4x8-bit		 ja_rd 4904d 07h /ion/trunk/vhdl/demo/
46 First version of cache: stub, 1-word cache
Stub cache tested on simulation and HW, just a stub
Adapted CPU stall logic to 1st version of cache
Adapted all other modules for compatibility with cache		 ja_rd 4904d 10h /ion/trunk/vhdl/demo/
40 pre-generated 'hello' demo updated ja_rd 4908d 13h /ion/trunk/vhdl/demo/
2 First commit (includes 'hello' demo) ja_rd 4913d 17h /ion/trunk/vhdl/demo/

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