OpenCores
URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] [ion/] [trunk/] [vhdl/] [demo/] - Rev 161

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
161 Added GPL license info to the vhdl headers
This project is becoming respectable :)
ja_rd 4781d 11h /ion/trunk/vhdl/demo/
138 updated simulation & synthesis pre-generated entities
('hello' code sample)
ja_rd 4789d 13h /ion/trunk/vhdl/demo/
136 Added debug output to synthesizable MPU template, and connected debug signals to LEDs ja_rd 4789d 13h /ion/trunk/vhdl/demo/
129 updated pregenerated demo ('hello') ja_rd 4792d 11h /ion/trunk/vhdl/demo/
119 Updated pre-generated simulation and synthesis demos ja_rd 4847d 13h /ion/trunk/vhdl/demo/
116 Updated demo 'top' file for DE-1 board
- Added reset button debouncing
- Added template for using different clock input
- Uses clock rate generic
ja_rd 4847d 14h /ion/trunk/vhdl/demo/
115 Updated Altera CSV file (pin location file) for DE-1 board
(Added 27MHz clock input)
ja_rd 4847d 16h /ion/trunk/vhdl/demo/
98 CPU rd and wr data address buses unified ja_rd 4880d 18h /ion/trunk/vhdl/demo/
94 Pregenerated demo 'hello' files updated ja_rd 4891d 14h /ion/trunk/vhdl/demo/
76 Adapted pregenerated vhdl files to latest changes ja_rd 4901d 12h /ion/trunk/vhdl/demo/
75 Added support for 8-bit-wide static memory (e.g. Flash)
Updated demo 'top' file to use the DE-1 onboard flash
ja_rd 4901d 12h /ion/trunk/vhdl/demo/
68 Updated pre-generated vhdl files ja_rd 4902d 04h /ion/trunk/vhdl/demo/
63 DE-1 demo top module:
added registers for SD interface, switches and 7-seg display
ja_rd 4902d 05h /ion/trunk/vhdl/demo/
59 cleaned up top vhdl module of demo
moved reset sync ff chain to top module
updated pre-generated demo file
ja_rd 4903d 18h /ion/trunk/vhdl/demo/
57 updated precompiled demo:
single 32-bit BROM instead of 4x8-bit
ja_rd 4904d 07h /ion/trunk/vhdl/demo/
46 First version of cache: stub, 1-word cache
Stub cache tested on simulation and HW, just a stub
Adapted CPU stall logic to 1st version of cache
Adapted all other modules for compatibility with cache
ja_rd 4904d 11h /ion/trunk/vhdl/demo/
40 pre-generated 'hello' demo updated ja_rd 4908d 13h /ion/trunk/vhdl/demo/
2 First commit (includes 'hello' demo) ja_rd 4913d 17h /ion/trunk/vhdl/demo/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.