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[/] [ion/] [trunk/] [vhdl/] [demo/] - Rev 243

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240 Added a few comments and minor changes to the DE-1 top entity. ja_rd 4241d 07h /ion/trunk/vhdl/demo/
234 Added a few GPIO registers to the SoC, updated the DE-1 'top' file to drive the SD interface with the GPIO signals. ja_rd 4242d 07h /ion/trunk/vhdl/demo/
233 Fixed top entity for De-1 demos: Bootstrap BRAM size is now taken from a constant in the obj code package. ja_rd 4260d 19h /ion/trunk/vhdl/demo/
227 Removed modules no longer used:
code_rom_pkg replaced by new package in SoC directory.
RS232 sub-modules replaced by new UART
ja_rd 4389d 13h /ion/trunk/vhdl/demo/
226 Updated demo and test bench to use new SoC entity. ja_rd 4389d 13h /ion/trunk/vhdl/demo/
214 Updated pre-generated 'Hello' demo, recompiled and retested with the latest changes. ja_rd 4400d 11h /ion/trunk/vhdl/demo/
200 CPU interrupt input changed to 8-bit vector
Other modules changed accordingly
Interrupts still missing; this is just preparing the interface
ja_rd 4714d 06h /ion/trunk/vhdl/demo/
193 Major test bench reorganization:
1.- TB now uses same object code as synthesizable demo.
2.- TB now simulates full MPU system.
3.- Console logging moved to TB package.
4.- Code sample makefiles and modelsim script updated accordingly.
ja_rd 4715d 22h /ion/trunk/vhdl/demo/
191 Separated object code stuff from mcu entity
Object code related stuff now lives in separate file
Makefiles for code samples updated accordingly
Old mcu template deprecated but still in place
ja_rd 4720d 07h /ion/trunk/vhdl/demo/
188 updated hello demo mpu file ja_rd 4729d 00h /ion/trunk/vhdl/demo/
162 Fixed stupid mistake in headers (date of project) ja_rd 4766d 04h /ion/trunk/vhdl/demo/
161 Added GPL license info to the vhdl headers
This project is becoming respectable :)
ja_rd 4766d 04h /ion/trunk/vhdl/demo/
138 updated simulation & synthesis pre-generated entities
('hello' code sample)
ja_rd 4774d 06h /ion/trunk/vhdl/demo/
136 Added debug output to synthesizable MPU template, and connected debug signals to LEDs ja_rd 4774d 06h /ion/trunk/vhdl/demo/
129 updated pregenerated demo ('hello') ja_rd 4777d 04h /ion/trunk/vhdl/demo/
119 Updated pre-generated simulation and synthesis demos ja_rd 4832d 07h /ion/trunk/vhdl/demo/
116 Updated demo 'top' file for DE-1 board
- Added reset button debouncing
- Added template for using different clock input
- Uses clock rate generic
ja_rd 4832d 08h /ion/trunk/vhdl/demo/
115 Updated Altera CSV file (pin location file) for DE-1 board
(Added 27MHz clock input)
ja_rd 4832d 10h /ion/trunk/vhdl/demo/
98 CPU rd and wr data address buses unified ja_rd 4865d 11h /ion/trunk/vhdl/demo/
94 Pregenerated demo 'hello' files updated ja_rd 4876d 08h /ion/trunk/vhdl/demo/

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