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[/] [ion/] [trunk/] [vhdl/] [tb/] - Rev 161

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Rev Log message Author Age Path
158 removed file from TB directory which was committed by mistake ja_rd 4782d 20h /ion/trunk/vhdl/tb/
157 Bug fix in the missing coprocesor exception.
The CPU was triggering a privilege exception for the mtc0 that went into user mode.
Logging HDL updated		 ja_rd 4784d 05h /ion/trunk/vhdl/tb/
152 Added R3000 compatible support for kernel/user state:
- Implemented KU/IE plus KUp/IEp and KUo/IEo status bits
- Updated startup and test code to account for changes
- Implemented bit DID NOT TEST rfe instruction (not used in code)
- Access to CP0 in user mode triggers 'CpU' trap
- Updated software simulator

Besides, the logging of HI/LO register changes has been temporarily disabled, there's an unfixed bug in it.		 ja_rd 4784d 15h /ion/trunk/vhdl/tb/
139 updated simulation & synthesis pre-generated entities
('hello' code sample)		 ja_rd 4789d 13h /ion/trunk/vhdl/tb/
138 updated simulation & synthesis pre-generated entities
('hello' code sample)		 ja_rd 4789d 13h /ion/trunk/vhdl/tb/
128 updated precompiled simulation testbench ja_rd 4792d 11h /ion/trunk/vhdl/tb/
126 added SDRAM verilog simulation model ja_rd 4792d 11h /ion/trunk/vhdl/tb/
119 Updated pre-generated simulation and synthesis demos ja_rd 4847d 13h /ion/trunk/vhdl/tb/
112 Updated simulation package for compatibility to new cache ja_rd 4847d 18h /ion/trunk/vhdl/tb/
98 CPU rd and wr data address buses unified ja_rd 4880d 18h /ion/trunk/vhdl/tb/
96 CPU rd and wr data address buses unified ja_rd 4880d 18h /ion/trunk/vhdl/tb/
94 Pregenerated demo 'hello' files updated ja_rd 4891d 14h /ion/trunk/vhdl/tb/
84 Added 'trigger address' for file logging to both the
vhdl TB and the python script		 ja_rd 4891d 14h /ion/trunk/vhdl/tb/
76 Adapted pregenerated vhdl files to latest changes ja_rd 4901d 12h /ion/trunk/vhdl/tb/
74 Fixed (harmless) error in simulation template 2 ja_rd 4901d 16h /ion/trunk/vhdl/tb/
68 Updated pre-generated vhdl files ja_rd 4902d 04h /ion/trunk/vhdl/tb/
60 Forgot to upload new TB package!!
Without this, simulations don't work...		 ja_rd 4902d 05h /ion/trunk/vhdl/tb/
47 Pre-generated simulation test benches updated ja_rd 4904d 10h /ion/trunk/vhdl/tb/
42 Added cache stub module, plus related test bench ja_rd 4908d 13h /ion/trunk/vhdl/tb/
36 pre-generated simulation test bench TB1 updated
for compatibility to other changes		 ja_rd 4908d 14h /ion/trunk/vhdl/tb/

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