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[/] [ion/] [trunk/] [vhdl/] [tb/] - Rev 240

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Rev	Log message	Author	Age	Path
237	Fixed test bench to work with latest modifications of SoC	ja_rd	4284d 05h	/ion/trunk/vhdl/tb/
226	Updated demo and test bench to use new SoC entity.	ja_rd	4432d 06h	/ion/trunk/vhdl/tb/
211	Included a simulated block of I/O regs in the test bench for easing some cache tests.	ja_rd	4443d 05h	/ion/trunk/vhdl/tb/
207	Simulation memories now modelled with shared variables and not signals. This improves simulation speed of large programs (e.g. Adventure) by orders of magnitude	ja_rd	4722d 01h	/ion/trunk/vhdl/tb/
206	Fixed SygnalSpy function calls for compatibility with older versions of Modelsim	ja_rd	4722d 01h	/ion/trunk/vhdl/tb/
205	Fixed bug in test bench interface to CPU	ja_rd	4743d 00h	/ion/trunk/vhdl/tb/
200	CPU interrupt input changed to 8-bit vector Other modules changed accordingly Interrupts still missing; this is just preparing the interface	ja_rd	4757d 00h	/ion/trunk/vhdl/tb/
194	Removed deprecated files from old TB version	ja_rd	4758d 16h	/ion/trunk/vhdl/tb/
193	Major test bench reorganization: 1.- TB now uses same object code as synthesizable demo. 2.- TB now simulates full MPU system. 3.- Console logging moved to TB package. 4.- Code sample makefiles and modelsim script updated accordingly.	ja_rd	4758d 16h	/ion/trunk/vhdl/tb/
158	removed file from TB directory which was committed by mistake	ja_rd	4810d 07h	/ion/trunk/vhdl/tb/
157	Bug fix in the missing coprocesor exception. The CPU was triggering a privilege exception for the mtc0 that went into user mode. Logging HDL updated	ja_rd	4811d 17h	/ion/trunk/vhdl/tb/
152	Added R3000 compatible support for kernel/user state: - Implemented KU/IE plus KUp/IEp and KUo/IEo status bits - Updated startup and test code to account for changes - Implemented bit DID NOT TEST rfe instruction (not used in code) - Access to CP0 in user mode triggers 'CpU' trap - Updated software simulator Besides, the logging of HI/LO register changes has been temporarily disabled, there's an unfixed bug in it.	ja_rd	4812d 02h	/ion/trunk/vhdl/tb/
139	updated simulation & synthesis pre-generated entities ('hello' code sample)	ja_rd	4817d 00h	/ion/trunk/vhdl/tb/
138	updated simulation & synthesis pre-generated entities ('hello' code sample)	ja_rd	4817d 00h	/ion/trunk/vhdl/tb/
128	updated precompiled simulation testbench	ja_rd	4819d 22h	/ion/trunk/vhdl/tb/
126	added SDRAM verilog simulation model	ja_rd	4819d 22h	/ion/trunk/vhdl/tb/
119	Updated pre-generated simulation and synthesis demos	ja_rd	4875d 01h	/ion/trunk/vhdl/tb/
112	Updated simulation package for compatibility to new cache	ja_rd	4875d 05h	/ion/trunk/vhdl/tb/
98	CPU rd and wr data address buses unified	ja_rd	4908d 05h	/ion/trunk/vhdl/tb/
96	CPU rd and wr data address buses unified	ja_rd	4908d 05h	/ion/trunk/vhdl/tb/

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[/] [ion/] [trunk/] [vhdl/] [tb/] - Rev 240

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