URL https://opencores.org/ocsvn/iso7816_3_master/iso7816_3_master/trunk

Subversion Repositories iso7816_3_master

[/] [iso7816_3_master/] - Rev 12

Rev	Log message	Author	Age	Path
12	pps sequence added to test bench endOfTx added to TxCore	acapola	4864d 11h	/iso7816_3_master/
11	added BSD licence header to files	acapola	4864d 15h	/iso7816_3_master/
10	communication direction probe added	acapola	4864d 17h	/iso7816_3_master/
9	parity convention fixed	acapola	4870d 13h	/iso7816_3_master/
8		acapola	4872d 12h	/iso7816_3_master/
7	- rx/tx use "cyclesPerEtu" input - "stopBit" status bit timing fixed - analyzer: "lastByte" and "bytesCnt" functional	acapola	4873d 11h	/iso7816_3_master/
6	analyzer added to test bench, not functional yet...	acapola	4874d 11h	/iso7816_3_master/
5	draft of t=0 protocol analyzer (to ease debuging, and eventually as an ip itself)	acapola	4875d 11h	/iso7816_3_master/
4	Basic test bench completed for T=0: a card send ATR, reader send a command TODO: add cycles/ETU management (start at 372, then adjust in case of PPS...)	acapola	4876d 12h	/iso7816_3_master/
3	initial draft, not functional yet	acapola	4883d 13h	/iso7816_3_master/
2		acapola	4883d 14h	/iso7816_3_master/
1	The project and the structure was created	root	4884d 10h	/iso7816_3_master/