URL https://opencores.org/ocsvn/iso7816_3_master/iso7816_3_master/trunk

Subversion Repositories iso7816_3_master

[/] [iso7816_3_master/] - Rev 15

Rev	Log message	Author	Age	Path
15	tpdu level tasks inverse convention	acapola	5018d 02h	/iso7816_3_master/
14	Task to send strings as bytes improved	acapola	5021d 02h	/iso7816_3_master/
13	Corrections in analyzer to handle TDi and historical bytes in ATR and PPS todo: handle inverse convention	acapola	5022d 05h	/iso7816_3_master/
12	pps sequence added to test bench endOfTx added to TxCore	acapola	5033d 02h	/iso7816_3_master/
11	added BSD licence header to files	acapola	5033d 05h	/iso7816_3_master/
10	communication direction probe added	acapola	5033d 07h	/iso7816_3_master/
9	parity convention fixed	acapola	5039d 03h	/iso7816_3_master/
8		acapola	5041d 02h	/iso7816_3_master/
7	- rx/tx use "cyclesPerEtu" input - "stopBit" status bit timing fixed - analyzer: "lastByte" and "bytesCnt" functional	acapola	5042d 02h	/iso7816_3_master/
6	analyzer added to test bench, not functional yet...	acapola	5043d 02h	/iso7816_3_master/
5	draft of t=0 protocol analyzer (to ease debuging, and eventually as an ip itself)	acapola	5044d 02h	/iso7816_3_master/
4	Basic test bench completed for T=0: a card send ATR, reader send a command TODO: add cycles/ETU management (start at 372, then adjust in case of PPS...)	acapola	5045d 02h	/iso7816_3_master/
3	initial draft, not functional yet	acapola	5052d 03h	/iso7816_3_master/
2		acapola	5052d 05h	/iso7816_3_master/
1	The project and the structure was created	root	5053d 00h	/iso7816_3_master/