OpenCores
URL https://opencores.org/ocsvn/iso7816_3_master/iso7816_3_master/trunk

Subversion Repositories iso7816_3_master

[/] [iso7816_3_master/] - Rev 17

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
17 yet another fix of the analyzer: ATR, and convention handling acapola 4843d 16h /iso7816_3_master/
16 just cosmetic acapola 4847d 16h /iso7816_3_master/
15 tpdu level tasks
inverse convention		 acapola 4848d 15h /iso7816_3_master/
14 Task to send strings as bytes improved acapola 4851d 15h /iso7816_3_master/
13 Corrections in analyzer to handle TDi and historical bytes in ATR and PPS
todo: handle inverse convention		 acapola 4852d 18h /iso7816_3_master/
12 pps sequence added to test bench
endOfTx added to TxCore		 acapola 4863d 14h /iso7816_3_master/
11 added BSD licence header to files acapola 4863d 18h /iso7816_3_master/
10 communication direction probe added acapola 4863d 20h /iso7816_3_master/
9 parity convention fixed acapola 4869d 16h /iso7816_3_master/
8 acapola 4871d 15h /iso7816_3_master/
7 - rx/tx use "cyclesPerEtu" input
- "stopBit" status bit timing fixed
- analyzer: "lastByte" and "bytesCnt" functional		 acapola 4872d 14h /iso7816_3_master/
6 analyzer added to test bench, not functional yet... acapola 4873d 14h /iso7816_3_master/
5 draft of t=0 protocol analyzer (to ease debuging, and eventually as an ip itself) acapola 4874d 15h /iso7816_3_master/
4 Basic test bench completed for T=0: a card send ATR, reader send a command
TODO: add cycles/ETU management (start at 372, then adjust in case of PPS...)		 acapola 4875d 15h /iso7816_3_master/
3 initial draft, not functional yet acapola 4882d 16h /iso7816_3_master/
2 acapola 4882d 17h /iso7816_3_master/
1 The project and the structure was created root 4883d 13h /iso7816_3_master/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.