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[/] [iso7816_3_master/] [trunk/] - Rev 18

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Rev Log message Author Age Path
18 A bunch of synthesis error/warning removed.
Master and analyzer synthesis OK on Spartan6 FPGA		 acapola 4826d 18h /iso7816_3_master/trunk/
17 yet another fix of the analyzer: ATR, and convention handling acapola 4843d 17h /iso7816_3_master/trunk/
16 just cosmetic acapola 4847d 17h /iso7816_3_master/trunk/
15 tpdu level tasks
inverse convention		 acapola 4848d 16h /iso7816_3_master/trunk/
14 Task to send strings as bytes improved acapola 4851d 15h /iso7816_3_master/trunk/
13 Corrections in analyzer to handle TDi and historical bytes in ATR and PPS
todo: handle inverse convention		 acapola 4852d 19h /iso7816_3_master/trunk/
12 pps sequence added to test bench
endOfTx added to TxCore		 acapola 4863d 15h /iso7816_3_master/trunk/
11 added BSD licence header to files acapola 4863d 19h /iso7816_3_master/trunk/
10 communication direction probe added acapola 4863d 20h /iso7816_3_master/trunk/
9 parity convention fixed acapola 4869d 17h /iso7816_3_master/trunk/
8 acapola 4871d 15h /iso7816_3_master/trunk/
7 - rx/tx use "cyclesPerEtu" input
- "stopBit" status bit timing fixed
- analyzer: "lastByte" and "bytesCnt" functional		 acapola 4872d 15h /iso7816_3_master/trunk/
6 analyzer added to test bench, not functional yet... acapola 4873d 15h /iso7816_3_master/trunk/
5 draft of t=0 protocol analyzer (to ease debuging, and eventually as an ip itself) acapola 4874d 15h /iso7816_3_master/trunk/
4 Basic test bench completed for T=0: a card send ATR, reader send a command
TODO: add cycles/ETU management (start at 372, then adjust in case of PPS...)		 acapola 4875d 16h /iso7816_3_master/trunk/
3 initial draft, not functional yet acapola 4882d 17h /iso7816_3_master/trunk/
2 acapola 4882d 18h /iso7816_3_master/trunk/
1 The project and the structure was created root 4883d 14h /iso7816_3_master/trunk/

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