URL https://opencores.org/ocsvn/iso7816_3_master/iso7816_3_master/trunk

Subversion Repositories iso7816_3_master

[/] [iso7816_3_master/] [trunk/] [test/] - Rev 12

Rev	Log message	Author	Age	Path
12	pps sequence added to test bench endOfTx added to TxCore	acapola	4887d 03h	/iso7816_3_master/trunk/test/
11	added BSD licence header to files	acapola	4887d 06h	/iso7816_3_master/trunk/test/
10	communication direction probe added	acapola	4887d 08h	/iso7816_3_master/trunk/test/
9	parity convention fixed	acapola	4893d 04h	/iso7816_3_master/trunk/test/
8		acapola	4895d 03h	/iso7816_3_master/trunk/test/
7	- rx/tx use "cyclesPerEtu" input - "stopBit" status bit timing fixed - analyzer: "lastByte" and "bytesCnt" functional	acapola	4896d 03h	/iso7816_3_master/trunk/test/
6	analyzer added to test bench, not functional yet...	acapola	4897d 03h	/iso7816_3_master/trunk/test/
5	draft of t=0 protocol analyzer (to ease debuging, and eventually as an ip itself)	acapola	4898d 03h	/iso7816_3_master/trunk/test/
4	Basic test bench completed for T=0: a card send ATR, reader send a command TODO: add cycles/ETU management (start at 372, then adjust in case of PPS...)	acapola	4899d 03h	/iso7816_3_master/trunk/test/
3	initial draft, not functional yet	acapola	4906d 04h	/iso7816_3_master/trunk/test/
2		acapola	4906d 06h	/iso7816_3_master/trunk/test/