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URL https://opencores.org/ocsvn/iso7816_3_master/iso7816_3_master/trunk

Subversion Repositories iso7816_3_master

[/] [iso7816_3_master/] [trunk/] [test/] - Rev 18

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Rev	Log message	Author	Age	Path
18	A bunch of synthesis error/warning removed. Master and analyzer synthesis OK on Spartan6 FPGA	acapola	4875d 05h	/iso7816_3_master/trunk/test/
17	yet another fix of the analyzer: ATR, and convention handling	acapola	4892d 04h	/iso7816_3_master/trunk/test/
16	just cosmetic	acapola	4896d 04h	/iso7816_3_master/trunk/test/
15	tpdu level tasks inverse convention	acapola	4897d 03h	/iso7816_3_master/trunk/test/
14	Task to send strings as bytes improved	acapola	4900d 02h	/iso7816_3_master/trunk/test/
13	Corrections in analyzer to handle TDi and historical bytes in ATR and PPS todo: handle inverse convention	acapola	4901d 05h	/iso7816_3_master/trunk/test/
12	pps sequence added to test bench endOfTx added to TxCore	acapola	4912d 02h	/iso7816_3_master/trunk/test/
11	added BSD licence header to files	acapola	4912d 06h	/iso7816_3_master/trunk/test/
10	communication direction probe added	acapola	4912d 07h	/iso7816_3_master/trunk/test/
9	parity convention fixed	acapola	4918d 03h	/iso7816_3_master/trunk/test/
8		acapola	4920d 02h	/iso7816_3_master/trunk/test/
7	- rx/tx use "cyclesPerEtu" input - "stopBit" status bit timing fixed - analyzer: "lastByte" and "bytesCnt" functional	acapola	4921d 02h	/iso7816_3_master/trunk/test/
6	analyzer added to test bench, not functional yet...	acapola	4922d 02h	/iso7816_3_master/trunk/test/
5	draft of t=0 protocol analyzer (to ease debuging, and eventually as an ip itself)	acapola	4923d 02h	/iso7816_3_master/trunk/test/
4	Basic test bench completed for T=0: a card send ATR, reader send a command TODO: add cycles/ETU management (start at 372, then adjust in case of PPS...)	acapola	4924d 03h	/iso7816_3_master/trunk/test/
3	initial draft, not functional yet	acapola	4931d 04h	/iso7816_3_master/trunk/test/
2		acapola	4931d 05h	/iso7816_3_master/trunk/test/

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