URL https://opencores.org/ocsvn/light8080/light8080/trunk

Subversion Repositories light8080

[/] [light8080/] - Rev 77

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Rev	Log message	Author	Age	Path
77	Fixed a few mistakes in the last code reorganization. Mostly bad paths but also a broken comment in the UART source...	ja_rd	4605d 21h	/light8080/
76	Corrected some minor issues in the core description document.	motilito	4612d 12h	/light8080/
75	Updated file list	ja_rd	4616d 04h	/light8080/
74	Testbenches for VHDL core moved to sw/tb. Added a mini-demo for the VHDL SoC on the DE-1 dev board. Added a mini-testbench for the VHDL SoC.	ja_rd	4616d 04h	/light8080/
73	New tool for VHDL object code constant generation. Old VHDL template tool moved to tools directory.	ja_rd	4616d 04h	/light8080/
72	Added specs document for VHDL/Verilog CPU core	ja_rd	4616d 04h	/light8080/
71	IMSAI manual removed, no longer used	ja_rd	4616d 04h	/light8080/
70	Added new VHDL SoC for demonstration purposes	ja_rd	4616d 04h	/light8080/
69	New simulation scripts for Modelsim in new separate directory. Includes old test benches for CPU VHDL core and new test benches for SoC VHDL core	ja_rd	4616d 04h	/light8080/
68	Corrected ihex2vlog tool to enable explicit RAM declaration for Spartan 2.	motilito	4627d 00h	/light8080/
67	Corrected bugs in the Small-C compiler.	motilito	4628d 02h	/light8080/
66	Adding interrupt example code to the Verilog implementation. An interrupt controller was added to the sample SOC module and a sample code was added to the "hello.c" example code.	motilito	4643d 00h	/light8080/
65	Adding Verilog initial version to the svn. Added the c80 Small-C compiler and AS80 assembler.	motilito	4654d 08h	/light8080/
64	BUG FIX: Flags CY and AC were not clear by logic instructions Added new flag to microcode: clr_acy Used new flag to clear AC and CY flags unconditonally Modified microcode for XR, OR and AN* to use new flag Modified microcode assembler to support new flag Addex explaination of new flag to documentation Old fix that worked only for XR* instructions removed Test bench tb0 modified to test CY clearance minimally (AC untested!) Pre-generated vhel test bench tb0 altered accordingly	ja_rd	4663d 08h	/light8080/
63	Modified syntax of ARGV parameter for compatibility to later versions of Perl	ja_rd	4663d 08h	/light8080/
62	Changed all hard tabs to spaces as preamble to a minor refactor	ja_rd	4663d 17h	/light8080/
61	Basic demo updated: main entity name changed to keep synthesis too happy	ja_rd	5031d 19h	/light8080/
60	Fixed nasty typo in pin constraints file (clock input)	ja_rd	5036d 00h	/light8080/
59	tabs to spaces	ja_rd	5060d 07h	/light8080/
58	tabs to spaces	ja_rd	5060d 08h	/light8080/

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[/] [light8080/] - Rev 77

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