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URL https://opencores.org/ocsvn/light8080/light8080/trunk

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[/] [light8080/] [trunk/] [vhdl/] - Rev 37

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Rev Log message Author Age Path
37 IMSAI monitor demo removed ja_rd 5588d 17h /light8080/trunk/vhdl/
36 CPM demo on cyclone 2 starter board
(work in progress)		 ja_rd 5588d 17h /light8080/trunk/vhdl/
35 CPM demo pin assignment file (Altera Quartus II) ja_rd 5588d 17h /light8080/trunk/vhdl/
34 rs232 sanitized and parametrized ja_rd 5588d 17h /light8080/trunk/vhdl/
31 New directory structure. root 5719d 20h /light8080/trunk/vhdl/
22 Totally changed -- vhdl code generated from a template
Interrupts tested from software using a simulated interrupt controller		 ja_rd 5740d 02h /trunk/vhdl/
21 Totally changed -- vhdl code generated from a template ja_rd 5740d 02h /trunk/vhdl/
20 VHDL template for test benches ja_rd 5740d 02h /trunk/vhdl/
19 Fixed a bug (intr pulses longer than 1 clock cycle failed in some circumstances)
Added an output to the core to mark the fetch cycle of all instructions
Started to add timing diagrams		 ja_rd 5740d 02h /trunk/vhdl/
13 Minor changes in embedded code changed (success code now stands out better visually)
Comments added explaining the TB mechanincs		 ja_rd 5826d 05h /trunk/vhdl/
12 Minor changes in embedded code changed (success code now stands out better visually) ja_rd 5826d 05h /trunk/vhdl/
11 typos fixed ja_rd 5826d 05h /trunk/vhdl/
10 minor edits, comments clarified ja_rd 5853d 19h /trunk/vhdl/
6 microcode bug in INR M, #setacy flag missing ja_rd 5923d 05h /trunk/vhdl/
4 light8080.vhdl

comments in header corrected (they were obsolete)		 ja_rd 6202d 08h /trunk/vhdl/
3 added author line and license file ja_rd 6208d 23h /trunk/vhdl/
2 initial commit ja_rd 6210d 09h /trunk/vhdl/

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