URL https://opencores.org/ocsvn/mem_ctrl/mem_ctrl/trunk

Subversion Repositories mem_ctrl

[/] [mem_ctrl/] [trunk/] [bench/] [verilog/] - Rev 10

Rev	Log message	Author	Age	Path
10	Fixed the TMS register setup to be tight and correct.	rudi	8327d 12h	/mem_ctrl/trunk/bench/verilog/
8	- Changed IO names to be more clear. - Uniquifyed define names to be core specific. - Removed "Refresh Early" configuration	rudi	8350d 06h	/mem_ctrl/trunk/bench/verilog/
4	1) Changed Directory Structure 2) Fixed several minor bugs	rudi	8362d 07h	/mem_ctrl/trunk/bench/verilog/