URL https://opencores.org/ocsvn/mem_ctrl/mem_ctrl/trunk

Subversion Repositories mem_ctrl

[/] [mem_ctrl/] [trunk/] [rtl/] [verilog/] - Rev 28

Rev	Log message	Author	Age	Path
28	New directory structure.	root	5572d 09h	/mem_ctrl/trunk/rtl/verilog/
22	Fixed several minor bugs, cleaned up the code further ...	rudi	8176d 21h	/mem_ctrl/trunk/rtl/verilog/
20	- Fixed combinatorial loops in synthesis - Fixed byte select bug	rudi	8208d 05h	/mem_ctrl/trunk/rtl/verilog/
19	* empty log message *	rudi	8217d 03h	/mem_ctrl/trunk/rtl/verilog/
18	- Made some changes not to expect clock during reset ...	rudi	8218d 07h	/mem_ctrl/trunk/rtl/verilog/
16	- More Synthesis cleanup, mostly for speed - Several bug fixes - Changed code to avoid auto-precharge and burst-terminate combinations (apparently illegal ?) Now we will do a manual precharge ...	rudi	8230d 08h	/mem_ctrl/trunk/rtl/verilog/
13	Fixed Register reads Tightened up timing for register rd/wr	rudi	8286d 07h	/mem_ctrl/trunk/rtl/verilog/
12	Changed Reset to be active high and async.	rudi	8296d 09h	/mem_ctrl/trunk/rtl/verilog/
11	* empty log message *	rudi	8309d 20h	/mem_ctrl/trunk/rtl/verilog/
9	Many fixes for minor bugs that showed up in gate level simulations.	rudi	8318d 07h	/mem_ctrl/trunk/rtl/verilog/
8	- Changed IO names to be more clear. - Uniquifyed define names to be core specific. - Removed "Refresh Early" configuration	rudi	8341d 02h	/mem_ctrl/trunk/rtl/verilog/
4	1) Changed Directory Structure 2) Fixed several minor bugs	rudi	8353d 02h	/mem_ctrl/trunk/rtl/verilog/