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[/] [minimips_superscalar/] - Rev 34

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Rev Log message Author Age Path
34 Delete delay_gate to upload a new one. mcafruni 1523d 13h /minimips_superscalar/
33 New syscop.vhd mcafruni 1523d 13h /minimips_superscalar/
32 Delete syscop to upload a new one. mcafruni 1523d 13h /minimips_superscalar/
31 New top module. mcafruni 1523d 13h /minimips_superscalar/
30 Delete top module to upload a new one. mcafruni 1523d 13h /minimips_superscalar/
29 New banc register file. mcafruni 1523d 13h /minimips_superscalar/
28 Delete banc.vhd to upload a new one. mcafruni 1523d 13h /minimips_superscalar/
27 New bench on P1 tag. mcafruni 1523d 13h /minimips_superscalar/
26 Delete bench to upload a new one. mcafruni 1523d 13h /minimips_superscalar/
25 New bench mcafruni 1523d 13h /minimips_superscalar/
24 Delete bench to upload a new one. mcafruni 1523d 13h /minimips_superscalar/
23 Moving the benchmarks folder into the trunk folder. mcafruni 1529d 08h /minimips_superscalar/
22 Wrong code. (fi0.bin) But revealed a bug that needs attention. mcafruni 1529d 08h /minimips_superscalar/
21 Correcting codes that work in behavioral simulation but cause problems with implementation. There must be more to be corrected yet. In analysis ... mcafruni 1529d 08h /minimips_superscalar/
20 I've uncommented wait statement so that the benchmark to be loaded into the simulation. mcafruni 1563d 20h /minimips_superscalar/
19 mcafruni 1897d 12h /minimips_superscalar/
18 clock_gate.vhd: removed.
minimips.vhd: Clock2 input is wrongly connected to the clock signal (Do not ask me how that happened. I'm sorry.). The right thing is to be connected to the clock2 signal. Adjusted.		 mcafruni 1897d 12h /minimips_superscalar/
17 Removing unnecessary clock-gate architecture. mcafruni 1897d 13h /minimips_superscalar/
16 FIR filter with 36 coefficients. (binary to run) mcafruni 1930d 22h /minimips_superscalar/
15 FIR filter with 36 coefficients. mcafruni 1930d 22h /minimips_superscalar/

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