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[/] [minimips_superscalar/] [tags/] - Rev 37

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Rev Log message Author Age Path
37 pc update. mcafruni 1579d 15h /minimips_superscalar/tags/
36 update pc mcafruni 1579d 15h /minimips_superscalar/tags/
35 New delay_gate.vhd mcafruni 1582d 11h /minimips_superscalar/tags/
34 Delete delay_gate to upload a new one. mcafruni 1582d 11h /minimips_superscalar/tags/
33 New syscop.vhd mcafruni 1582d 11h /minimips_superscalar/tags/
32 Delete syscop to upload a new one. mcafruni 1582d 11h /minimips_superscalar/tags/
31 New top module. mcafruni 1582d 11h /minimips_superscalar/tags/
30 Delete top module to upload a new one. mcafruni 1582d 11h /minimips_superscalar/tags/
29 New banc register file. mcafruni 1582d 11h /minimips_superscalar/tags/
28 Delete banc.vhd to upload a new one. mcafruni 1582d 11h /minimips_superscalar/tags/
27 New bench on P1 tag. mcafruni 1582d 11h /minimips_superscalar/tags/
26 Delete bench to upload a new one. mcafruni 1582d 11h /minimips_superscalar/tags/
23 Moving the benchmarks folder into the trunk folder. mcafruni 1588d 05h /minimips_superscalar/tags/
22 Wrong code. (fi0.bin) But revealed a bug that needs attention. mcafruni 1588d 06h /minimips_superscalar/tags/
21 Correcting codes that work in behavioral simulation but cause problems with implementation. There must be more to be corrected yet. In analysis ... mcafruni 1588d 06h /minimips_superscalar/tags/
19 mcafruni 1956d 10h /minimips_superscalar/tags/
18 clock_gate.vhd: removed.
minimips.vhd: Clock2 input is wrongly connected to the clock signal (Do not ask me how that happened. I'm sorry.). The right thing is to be connected to the clock2 signal. Adjusted.		 mcafruni 1956d 10h /minimips_superscalar/tags/
16 FIR filter with 36 coefficients. (binary to run) mcafruni 1989d 20h /minimips_superscalar/tags/
15 FIR filter with 36 coefficients. mcafruni 1989d 20h /minimips_superscalar/tags/
14 Buble Sort algorithm. Four totally disorderly numbers are sorted in ascending order. Worst performance algorithm. mcafruni 1993d 14h /minimips_superscalar/tags/

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