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[/] [minimips_superscalar/] [tags/] - Rev 40

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Rev Log message Author Age Path
37 pc update. mcafruni 1529d 12h /minimips_superscalar/tags/
36 update pc mcafruni 1529d 12h /minimips_superscalar/tags/
35 New delay_gate.vhd mcafruni 1532d 08h /minimips_superscalar/tags/
34 Delete delay_gate to upload a new one. mcafruni 1532d 08h /minimips_superscalar/tags/
33 New syscop.vhd mcafruni 1532d 08h /minimips_superscalar/tags/
32 Delete syscop to upload a new one. mcafruni 1532d 08h /minimips_superscalar/tags/
31 New top module. mcafruni 1532d 08h /minimips_superscalar/tags/
30 Delete top module to upload a new one. mcafruni 1532d 08h /minimips_superscalar/tags/
29 New banc register file. mcafruni 1532d 08h /minimips_superscalar/tags/
28 Delete banc.vhd to upload a new one. mcafruni 1532d 08h /minimips_superscalar/tags/
27 New bench on P1 tag. mcafruni 1532d 08h /minimips_superscalar/tags/
26 Delete bench to upload a new one. mcafruni 1532d 08h /minimips_superscalar/tags/
23 Moving the benchmarks folder into the trunk folder. mcafruni 1538d 02h /minimips_superscalar/tags/
22 Wrong code. (fi0.bin) But revealed a bug that needs attention. mcafruni 1538d 02h /minimips_superscalar/tags/
21 Correcting codes that work in behavioral simulation but cause problems with implementation. There must be more to be corrected yet. In analysis ... mcafruni 1538d 02h /minimips_superscalar/tags/
19 mcafruni 1906d 07h /minimips_superscalar/tags/
18 clock_gate.vhd: removed.
minimips.vhd: Clock2 input is wrongly connected to the clock signal (Do not ask me how that happened. I'm sorry.). The right thing is to be connected to the clock2 signal. Adjusted.		 mcafruni 1906d 07h /minimips_superscalar/tags/
16 FIR filter with 36 coefficients. (binary to run) mcafruni 1939d 17h /minimips_superscalar/tags/
15 FIR filter with 36 coefficients. mcafruni 1939d 17h /minimips_superscalar/tags/
14 Buble Sort algorithm. Four totally disorderly numbers are sorted in ascending order. Worst performance algorithm. mcafruni 1943d 11h /minimips_superscalar/tags/

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