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[/] [minsoc/] - Rev 143

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Rev	Log message	Author	Age	Path
143	Compiling firmwares in board configuration scripts instead of on global minsoc setup.	rfajardo	4745d 20h	/minsoc/
142	Updating configure.sh: 1) we don't patch the trunk version. 2) it is better to re-compile the firmwares on reconfiguration. So compiling firmwares went to configure scripts instead. backend/xxx/configure: compiling firmwares here now.	rfajardo	4745d 20h	/minsoc/
141	Merging with rc-1.0 revision 140. I doubt rc-1.0 will still change much in the last days.	rfajardo	4745d 20h	/minsoc/
140	Including required modules for verilator simulation.	rfajardo	4745d 21h	/minsoc/
139	Creating a verilator branche.	rfajardo	4745d 21h	/minsoc/
138	DIR_TO_INSTALL creation using wizard	ConX.	4746d 09h	/minsoc/
137	Removing uncomplete support for ml509 and not working support for spartan3e_starter_kit_eth (area constraint cannot be reached).	rfajardo	4746d 20h	/minsoc/
136	Installation on Ubuntu-11.10 has shown that a binary called makeinfo is required to install GDB. This binary can be installed on Ubuntu by installing the package texinfo.	rfajardo	4753d 16h	/minsoc/
135	Installation on Ubuntu-11.10 has shown that package texinfo is required to compiled GDB. This package installs the binary makeinfo.	rfajardo	4753d 16h	/minsoc/
134	run_sim.bat for ModelSim updated to acquire the firmware_size for command line input when running the testbench.	rfajardo	4760d 20h	/minsoc/
133	Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock again. Applying Rubén Diez patch to avoid warnings on firmware load for simulation.	rfajardo	4760d 21h	/minsoc/
132	ModelSim simulation, running top_module minsoc_bench_clock now, instead of minsoc_bench.	rfajardo	4764d 17h	/minsoc/
131	Renaming testbench modules. Adding to ifdefs without which the testbench generation can fail.	rfajardo	4764d 17h	/minsoc/
130	minsoc_bench.v: task test_eth has to be phased out together with the ETHERNET definition. If there is no ETHERNET, test_eth cannot be defined.	rfajardo	4764d 19h	/minsoc/
129	Removing bugs introduced when splitting clocks and reset. 1) NEGATIVE_RESET or POSITIVE_RESET were missing as definition on minsoc_bench_clock.v (include minsoc_defines.v). 2) wait for reset on minsoc_bench.v to assert design_ready	rfajardo	4765d 06h	/minsoc/
128	Outsourcing clocks and reset generations from minsoc_bench.v to minsoc_bench_clock.v.	rfajardo	4765d 07h	/minsoc/
127	Removing redundant simulation output.	rfajardo	4765d 13h	/minsoc/
126	Updating information about simulation time for Ethernet test.	rfajardo	4765d 13h	/minsoc/
125	Adjusting testbench messages. Creating tasks for firmware tests.	rfajardo	4765d 14h	/minsoc/
124	Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart or ethernet have to be tested. If yes, it checks the behavior of the enclosed firmwares. If not, simulation simply runs forever.	rfajardo	4765d 15h	/minsoc/

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[/] [minsoc/] - Rev 143

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