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[/] [minsoc/] [branches/] [rc-1.0/] [sim/] [run/] - Rev 136

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Rev	Log message	Author	Age	Path
133	Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock again. Applying Rubén Diez patch to avoid warnings on firmware load for simulation.	rfajardo	4747d 06h	/minsoc/branches/rc-1.0/sim/run/
109	Creating a branche for release candidate 1.0.	rfajardo	4758d 20h	/minsoc/branches/rc-1.0/sim/run/
104	Enabling modelsim simulation for current project definition. vhdl and verilog projects have to be separated: -prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS. -Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently. -prj/scripts/simprj.sh splitted in: -simvhdl.sh -simverilog.sh (they generate the input files in the right format for simulation tools)	rfajardo	4766d 05h	/minsoc/branches/rc-1.0/sim/run/
85	Central project definition under prj. Synthesis and simulation take their project files from here.	rfajardo	4809d 00h	/minsoc/branches/rc-1.0/sim/run/
60	Selection of memory model or implementation memory is now made on minsoc_bench_defines.v. It is done by a definition instead of including different files for simulation. minsoc_bench_defines.v definition of reset level was not correct. It based the level decision on defineds POSITIVE_RESET or NEGATIVE_RESET, which couldn't be defined by then, since minsoc_defines.v is not included in minsoc_bench_defines.v. The decision has been moved to minsoc_bench.v and made a localparam instead of a definition.	rfajardo	4939d 17h	/minsoc/branches/rc-1.0/sim/run/
34	start_server changed: '-t' option of adv_jtag_bridge for vpi connection on simulation removed. or1200_v3 will not pass on CPU self test. FAQ completed with asked questions since Februrary 2010. INSTALL informs bsdl files only have to be copied to home directory for Xilinx devices. synthesis_examples title includes Minimal OpenRISC System on Chip.	rfajardo	5135d 01h	/minsoc/branches/rc-1.0/sim/run/
30	minsoc SoC documentation had 2 small typo corrections. Performance penalty due to addition of register addresses was a wrong assumption. On project description "is composed by" -> "consists of". Thanks to Wojciech A. Koszek. howto, at some places the howto did not tell the path from the files being talked about. I tried to always specify the path for every commented file. Scripts for running the simulation called bash instead of sh. For compatibility reasons sh is now used, this should affect noone. Scripts do not use bash specific commands and generally every UNIX like computer has sh. Thanks again to Wojciech A. Koszek, who adapted that to port it to FreeBSD.	rfajardo	5255d 06h	/minsoc/branches/rc-1.0/sim/run/
17	Ethernet testbench speed penalty solved. Now Ethernet of testbench and minsoc can be enabled by only uncommenting `define ETHERNET on minsoc_defines.v. send_mac, get_mac and uart_send tasks have been included/improved. Also a testbench, which works for both included firmwares is added. (eth and uart) If ETHERNET is defined for the SoC, both firmwares will complete successfully. If not, the eth firmware will stall when trying to access the Ethernet module.	rfajardo	5467d 01h	/minsoc/branches/rc-1.0/sim/run/
2	First commit of project. Beta status: -testbench: working -firmware: working -RTL: Working for: Xilinx Spartan-3A DSP Development Kit	rfajardo	5527d 04h	/minsoc/branches/rc-1.0/sim/run/

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