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[/] [minsoc/] [branches/] [verilator/] - Rev 164

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Rev Log message Author Age Path
153 Updating installation script to download minsoc from this branche, verilator, instead of rc-1.0. rfajardo 4725d 14h /minsoc/branches/verilator/
140 Including required modules for verilator simulation. rfajardo 4731d 15h /minsoc/branches/verilator/
139 Creating a verilator branche. rfajardo 4731d 15h /minsoc/branches/verilator/
138 DIR_TO_INSTALL creation using wizard ConX. 4732d 04h /minsoc/branches/rc-1.0/
137 Removing uncomplete support for ml509 and not working support for spartan3e_starter_kit_eth (area constraint cannot be reached). rfajardo 4732d 14h /minsoc/branches/rc-1.0/
136 Installation on Ubuntu-11.10 has shown that a binary called makeinfo is required to install GDB. This binary can be installed on Ubuntu by installing the package texinfo. rfajardo 4739d 10h /minsoc/branches/rc-1.0/
134 run_sim.bat for ModelSim updated to acquire the firmware_size for command line input when running the testbench. rfajardo 4746d 14h /minsoc/branches/rc-1.0/
133 Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock again.

Applying Rubén Diez patch to avoid warnings on firmware load for simulation.		 rfajardo 4746d 15h /minsoc/branches/rc-1.0/
132 ModelSim simulation, running top_module minsoc_bench_clock now, instead of minsoc_bench. rfajardo 4750d 11h /minsoc/branches/rc-1.0/
131 Renaming testbench modules. Adding to ifdefs without which the testbench generation can fail. rfajardo 4750d 11h /minsoc/branches/rc-1.0/
130 minsoc_bench.v: task test_eth has to be phased out together with the ETHERNET definition. If there is no ETHERNET, test_eth cannot be defined. rfajardo 4750d 14h /minsoc/branches/rc-1.0/
129 Removing bugs introduced when splitting clocks and reset.
1) NEGATIVE_RESET or POSITIVE_RESET were missing as definition on minsoc_bench_clock.v (include minsoc_defines.v).
2) wait for reset on minsoc_bench.v to assert design_ready		 rfajardo 4751d 01h /minsoc/branches/rc-1.0/
128 Outsourcing clocks and reset generations from minsoc_bench.v to minsoc_bench_clock.v. rfajardo 4751d 01h /minsoc/branches/rc-1.0/
127 Removing redundant simulation output. rfajardo 4751d 08h /minsoc/branches/rc-1.0/
126 Updating information about simulation time for Ethernet test. rfajardo 4751d 08h /minsoc/branches/rc-1.0/
125 Adjusting testbench messages. Creating tasks for firmware tests. rfajardo 4751d 08h /minsoc/branches/rc-1.0/
124 Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart or ethernet have to be tested. If yes, it checks the behavior of the enclosed firmwares. If not, simulation simply runs forever. rfajardo 4751d 10h /minsoc/branches/rc-1.0/
123 Renaming reg final to firmware_size. Final is a keyword for Verilator. rfajardo 4751d 15h /minsoc/branches/rc-1.0/
122 Renaming minsoc-configure.sh to minsoc-setup.sh. rfajardo 4757d 04h /minsoc/branches/rc-1.0/
121 Asserting svn:executable properties of modelsim/*.bat scripts.

Including corrected patch for advanced debug system watchpoints under utils/setup. Configure script updated to use this instead of advanced debug system patches. This will remain so until the patch is corrected. The previous line still has the correct command.		 rfajardo 4757d 06h /minsoc/branches/rc-1.0/

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