| Rev |
Log message |
Author |
Age |
Path |
| 57 |
If a FPGA manufacturer is selected, the FPGA families of other manufacturers are automatically ignored.
Some updated to comments.
CLOCK_DIVISOR back to 5. The number does not matter much, but 1 is a bad standard number, since it should never be selected. Comment says, use NO_CLOCK_DIVISION instead.
Changing standard FPGA back to Xilinx and Spartan3A. I'm only doing this because the synthesis examples page of wiki still assume this FPGA to be standardly selected. |
rfajardo |
4945d 02h |
/minsoc/branches/verilator/ |
| 56 |
Macros for all Altera family devices and pll instantiation |
javieralso |
4952d 01h |
/minsoc/branches/verilator/ |
| 55 |
Adjusting Makefiles to compile correctly with new firmware updates.
1) except.o not included into libsupport.a.
2) libsupport.a linked to except.o, now in correct order: ld libsupport.a except.o -o executable (not the other way around)
3) int.c was not being compiled because of a #ifdef which is not set anywhere |
rfajardo |
4953d 09h |
/minsoc/branches/verilator/ |
| 54 |
Moving spr_defs.h to or1200.h |
ConX. |
4953d 11h |
/minsoc/branches/verilator/ |
| 53 |
Indentation, deleting redundant files and adding externals |
ConX. |
4953d 12h |
/minsoc/branches/verilator/ |
| 52 |
Altera ALTPLL Megafunction Instantiation |
javieralso |
4962d 03h |
/minsoc/branches/verilator/ |
| 51 |
sw/support/uart.c: Changing the order of writes to the Divisor Latch of UART. (Thanks Ramkumar) |
rfajardo |
4968d 15h |
/minsoc/branches/verilator/ |
| 50 |
Removing unused firmware files, respective to or1ksim actually.
Removing the inclusion of the removed file mc.h in reset.S, probably required by or1ksim at some point.
Reworked except.S to use a macro instead of repeating the same procedure 16 times or so. Explanation added to the macro as a leading comment. |
rfajardo |
4980d 12h |
/minsoc/branches/verilator/ |
| 49 |
Language correction for README.txt. |
rfajardo |
4982d 09h |
/minsoc/branches/verilator/ |
| 48 |
Clear some old docs that are already ported to MinSOC's Wiki |
ConX. |
4982d 11h |
/minsoc/branches/verilator/ |
| 47 |
Firmware updated to work with gcc-4.5. It is actually working just fine and gcc-4.5 assembly code seems a lot cleaner.
I noticed that by increasing the free stack space for the interrupt handler by 130 made the resulting firmware not work. I assume it is because 130 is not aligned 130%4 = 2 and the stack simply does not work then. Instead I'm freeing the previous 116 plus 128 (for 32 registers as mentioned by Jeremy) and it works. |
rfajardo |
4983d 09h |
/minsoc/branches/verilator/ |
| 46 |
Including an explanation of what has to be updated on gpio to port it smoothly to minsoc. |
rfajardo |
4983d 13h |
/minsoc/branches/verilator/ |
| 45 |
A more stable version |
ConX. |
4984d 05h |
/minsoc/branches/verilator/ |
| 44 |
Fixing some bugs. But it still works only in Debian/Ubuntu |
ConX. |
4984d 06h |
/minsoc/branches/verilator/ |
| 43 |
Making some changes to MinSOC install script |
ConX. |
4985d 03h |
/minsoc/branches/verilator/ |
| 41 |
Including setup scripts to install all required tools to work with minsoc and to download all required sources. Thanks for the contribution of Xanthopoulos Constantinos. |
rfajardo |
4989d 09h |
/minsoc/branches/verilator/ |
| 40 |
Commiting a contributions directory, which has raw contributions of users. These contributions still have to be adapted to the system in order to work well. However, some users are certainly able to work with these versions.
FAQ: -added new idea to circumvent onboard DLC9 cable problem for adv_jtag_bridge
INSTALL: -gives a hint on how to install the system for Windows
HOWTO: -explains what a ucf file is and how to create it
backend: now we have the first contribution of a ucf file for the ML509 board (thanks to Matthew Hick)
Documentation: THESIS.txt explains to users, willing to tweak/understand the inner behavior of the OR1200 implementation of OpenRISC, what to read in order to get this information. |
rfajardo |
4995d 08h |
/minsoc/branches/verilator/ |
| 39 |
FAQ:
-Adv_jtag_bridge self test fails?
-included now SoC flow mistakes
-forgetting to upload the bitfile
-leaving clock unconnected
-older information is now under "Known Issues" right below of SoC flow mistakes
Software:
-eth: included eth.h is from drivers and not from this directory. eth.h from this directory is old and has been removed.
-uart: included uart.h is from drivers and not from this directory. uart.h from this directory is old and has been removed. |
rfajardo |
5060d 01h |
/minsoc/branches/verilator/ |
| 38 |
Small update to HOWTO: advices now to also include the ucf (pinout) file, for forgetful people :-).
FAQ: Added another option (hint) as a solution for people with on-board Xilinx USB cables, which do not reset.
uart.c: now uses the IRQ line definition instead of the line number directly. |
rfajardo |
5095d 00h |
/minsoc/branches/verilator/ |
| 37 |
README.txt added, describing the installation and set-up processes. Also describing to use the FAQ or forum when you have problems and finally to read minsoc.pdf (the documentation) to understand the system after everything works, to know what to do next.
Clean-up of sw/utils, removing unused sources and files.
Update of sw/drivers/eth.c, direct casting to avoid compile warnings.
FAQ extended and with more links to the threads giving the solutions.
Synthesis examples inform that the firmware tweak for Spartan3E Starter Kit using Ethernet only works for system version up to 35.
minsoc.pdf and webpage now uses FPGA generic and specific codes instead of FPGA independent and dependent codes, because it suits it better. |
rfajardo |
5125d 11h |
/minsoc/branches/verilator/ |
