| Rev |
Log message |
Author |
Age |
Path |
| 139 |
Creating a verilator branche. |
rfajardo |
5129d 06h |
/minsoc/branches/verilator/backend/ |
| 137 |
Removing uncomplete support for ml509 and not working support for spartan3e_starter_kit_eth (area constraint cannot be reached). |
rfajardo |
5130d 05h |
/minsoc/branches/rc-1.0/backend/ |
| 124 |
Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart or ethernet have to be tested. If yes, it checks the behavior of the enclosed firmwares. If not, simulation simply runs forever. |
rfajardo |
5149d 00h |
/minsoc/branches/rc-1.0/backend/ |
| 118 |
Configure scripts for Xilinx devices updated. All of them require to update or1200_defines.v. The non-standard part uses now the variable $BOARD to print that this board require non-standard update of files. |
rfajardo |
5154d 23h |
/minsoc/branches/rc-1.0/backend/ |
| 117 |
spartan3e_starter_kit designs require DUALPORT from or1200_defines.v to be active instead of GENERIC. |
rfajardo |
5155d 00h |
/minsoc/branches/rc-1.0/backend/ |
| 116 |
Configure scripts were trying to copy/patch projects files before creating them. Ordering is correct now. |
rfajardo |
5155d 01h |
/minsoc/branches/rc-1.0/backend/ |
| 113 |
minsoc-install.sh & minsoc-configure.sh:
-aware of location of configure.sh script
configure.sh:
-does not block on patch error
spartan3e_starter_kit & spartan3e_starter_kit_eth:
-or1200_defines.v updated
prj:
-src/blackboxes/or1200_top.v adjusted to or1200_rel1
-Makefile had a typo regarding altera vhdl files |
rfajardo |
5155d 02h |
/minsoc/branches/rc-1.0/backend/ |
| 110 |
Fixing several minor issues with the system:
-minsoc-install splitted into installation and configuration
-minsoc-configure.sh can be used to configure a fresh checked out system
-configure script used by both minsoc-configure.sh and minsoc-install.sh to configure
-rtl/verilog: svn externals fixed
-or1200 rolled back to release-1.0
-prj/scripts:
-Makefile has been used by simulation to differentiate project definition of vhdl and verilog files
-Altera was differentiating it in script
-now there are two scripts, one for vhdl and another for verilog. The differentiation occurs in Makefile as for simulation.
-altera_3c25_board/configure scripts had to be updated, vprj and vhdprj file extensions used to differentiate Verilog and VHDL project files.
-prj/src: or1200_top.prj downdated to definition of or1200_v1 |
rfajardo |
5155d 18h |
/minsoc/branches/rc-1.0/backend/ |
| 109 |
Creating a branche for release candidate 1.0. |
rfajardo |
5155d 20h |
/minsoc/branches/rc-1.0/backend/ |
| 105 |
Updating configure scripts to copy Windows synthesis launch script setup.bat from either minsoc/syn/altera or minsoc/syn/xilinx to minsoc/syn. |
rfajardo |
5156d 07h |
/minsoc/trunk/backend/ |
| 99 |
backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails. |
rfajardo |
5200d 06h |
/minsoc/trunk/backend/ |
| 97 |
As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. |
rfajardo |
5200d 07h |
/minsoc/trunk/backend/ |
| 96 |
Some files needed for Altera synthesis |
javieralso |
5200d 18h |
/minsoc/trunk/backend/ |
| 95 |
Makefile for Altera FPGAs fixed |
javieralso |
5201d 21h |
/minsoc/trunk/backend/ |
| 93 |
Support for Altera synthesis. It needs some tune, but it works fine |
javieralso |
5204d 08h |
/minsoc/trunk/backend/ |
| 92 |
backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it would be best if we used a patching system here. But for now, I copied the new files and made the necessary changes to fit the system into the target boards. |
rfajardo |
5205d 06h |
/minsoc/trunk/backend/ |
| 88 |
Project structure, Xilinx Makefiles and simulation working. |
rfajardo |
5205d 23h |
/minsoc/trunk/backend/ |
| 87 |
Synchronizing scripts to behave exactly the same. |
rfajardo |
5206d 00h |
/minsoc/trunk/backend/ |
| 86 |
Updating configure script messages. |
rfajardo |
5206d 00h |
/minsoc/trunk/backend/ |
| 85 |
Central project definition under prj. Synthesis and simulation take their project files from here. |
rfajardo |
5206d 00h |
/minsoc/trunk/backend/ |
