URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

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[/] [minsoc/] [branches/] [verilator/] [backend/] [altera_3c25_board/] - Rev 97

Rev	Log message	Author	Age	Path
97	As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board.	rfajardo	4661d 11h	/minsoc/branches/verilator/backend/altera_3c25_board/
96	Some files needed for Altera synthesis	javieralso	4661d 22h	/minsoc/branches/verilator/backend/altera_3c25_board/
95	Makefile for Altera FPGAs fixed	javieralso	4663d 01h	/minsoc/branches/verilator/backend/altera_3c25_board/
93	Support for Altera synthesis. It needs some tune, but it works fine	javieralso	4665d 12h	/minsoc/branches/verilator/backend/altera_3c25_board/