| Rev |
Log message |
Author |
Age |
Path |
| 27 |
Simulation library fpga_memory_primitives.v had an issue with its lpm_ram_dq module, which did not output its data.
The data was being output to doq instead of q, the declared output. doq was also not defined anywhere else.
Icarus Verilog did not detect this, because Verilog-2001 allows internal wires to be used without being defined. To detect this errors, one can define "`default_nettype none". After doing this, Icarus Verilog detected that error and nothing else.
doq changed to q, error corrected. |
rfajardo |
5318d 06h |
/minsoc/branches/verilator/bench/verilog/ |
| 17 |
Ethernet testbench speed penalty solved. Now Ethernet of testbench and minsoc can be enabled by only uncommenting `define ETHERNET on minsoc_defines.v.
send_mac, get_mac and uart_send tasks have been included/improved. Also a testbench, which works for both included firmwares is added. (eth and uart)
If ETHERNET is defined for the SoC, both firmwares will complete successfully. If not, the eth firmware will stall when trying to access the Ethernet module. |
rfajardo |
5472d 06h |
/minsoc/branches/verilator/bench/verilog/ |
| 11 |
External interrupt processing was being run multiple times because:
-external level interrupts have to be cleared
-internal interrupt status register has to be cleared
Since internal interrupt status register was being cleared before external level interrupts clearance, these internal interrupt status was being overwritten inbetween.
Solution:
-move status register reset to end of interrupt handler instead of beginning.
Testbench signal uart_srx initialized now. |
rfajardo |
5497d 06h |
/minsoc/branches/verilator/bench/verilog/ |
| 10 |
Added a file containing models for each FPGA memory instances used in or1200. The file is in bench/verilog/sim_lib/fpga_memory_primitives.v.
With it, people who change the or1200_defines.v inside of the project structure will still be able to simulate, using house-made models, not from manufacturers.
minsoc_bench.v had to be extended by the task, init_fpga_memory, to initialize the dual or two port memories instances of or1200. This has to be done based on the type of memory used, so many different instantiations based on definitions. Somehow or1200 expects all memory values to be 0 upon start, so this is necessary. |
rfajardo |
5511d 05h |
/minsoc/branches/verilator/bench/verilog/ |
| 9 |
Tiny change to testbench gain:
-uart_srx is now reg for future testbench serial input to SoC. |
rfajardo |
5513d 04h |
/minsoc/branches/verilator/bench/verilog/ |
| 8 |
Cosmetic changes to minsoc_bench.v:
-reset and clock initialization are included into the main initial block, it had an own block before |
rfajardo |
5513d 04h |
/minsoc/branches/verilator/bench/verilog/ |
| 7 |
Some changes:
-wb_cabs removed from minsoc_top.v and minsoc_tc_top.v
-added reset polarity control to minsoc_defines.v through:
-POSITIVE_RESET
-NEGATIVE_RESET
-minsoc_onchip_ram_top.v does not use
minsoc_onchip_ram.v oe signals (output enable) anymore,
which are implemented as tristate buffers. Now
minsoc_onchip_ram_top.v has a generated MUX, which
has an arbitrary number of inputs and 1 output.
Input are the internal output of the onchip_rams,
output the wb_dat_o. |
rfajardo |
5518d 04h |
/minsoc/branches/verilator/bench/verilog/ |
| 4 |
minsoc_bench.v had a big memory declaration to load the firmware, which was not necessary.
jp-io-vpi.vpi has to be compiled for different systems so removed from the project. Documentation now explains how to do it.
Documentation now includes:
-vpi module compilation
-gdb patch for adv_jtag_bridge
-ideas for future work on minsoc (To Do v.2) |
rfajardo |
5528d 10h |
/minsoc/branches/verilator/bench/verilog/ |
| 2 |
First commit of project. Beta status:
-testbench: working
-firmware: working
-RTL: Working for: Xilinx Spartan-3A DSP Development Kit |
rfajardo |
5532d 09h |
/minsoc/branches/verilator/bench/verilog/ |
