URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [verilator/] [bench/] [verilog/] [vpi/] - Rev 153

Rev	Log message	Author	Age	Path
139	Creating a verilator branche.	rfajardo	4736d 15h	/minsoc/branches/verilator/bench/verilog/vpi/
109	Creating a branche for release candidate 1.0.	rfajardo	4763d 06h	/minsoc/branches/verilator/bench/verilog/vpi/
71	Modelsim whines about missing timescales: -minsoc_bench.v, minsoc_memory_model.v and dbg_comm_vpi.v updated to include timescale.v modelsim simulation working under Windows. Modelsim PE Student Edition 10.0a Simulation<->adv_jtag_bridge<->gdb communication not working perfectly. I believe VPI module has to be recompiled, used pre-compiled one for now.	rfajardo	4932d 15h	/minsoc/branches/verilator/bench/verilog/vpi/
4	minsoc_bench.v had a big memory declaration to load the firmware, which was not necessary. jp-io-vpi.vpi has to be compiled for different systems so removed from the project. Documentation now explains how to do it. Documentation now includes: -vpi module compilation -gdb patch for adv_jtag_bridge -ideas for future work on minsoc (To Do v.2)	rfajardo	5527d 15h	/minsoc/branches/verilator/bench/verilog/vpi/
2	First commit of project. Beta status: -testbench: working -firmware: working -RTL: Working for: Xilinx Spartan-3A DSP Development Kit	rfajardo	5531d 14h	/minsoc/branches/verilator/bench/verilog/vpi/