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17 Ethernet testbench speed penalty solved. Now Ethernet of testbench and minsoc can be enabled by only uncommenting `define ETHERNET on minsoc_defines.v.

send_mac, get_mac and uart_send tasks have been included/improved. Also a testbench, which works for both included firmwares is added. (eth and uart)

If ETHERNET is defined for the SoC, both firmwares will complete successfully. If not, the eth firmware will stall when trying to access the Ethernet module.		 rfajardo 5479d 06h /minsoc/branches/verilator/doc/
12 1) spi_top.v:
-TX_NEGEDGE bug reported and recommended solution by Blaise Gassend. (Thank you)
2) minsoc howto extended to:
-synthesis of minsoc for Spartan3E Starter Kit with Ethernet
3) spartan3e_starter_kit.ucf changed:
-it had problems regarding pin definitions and IO logic types for mapping and place&route. Working flawless now.		 rfajardo 5497d 02h /minsoc/branches/verilator/doc/
6 No implementation relevant changes.

Testbench used generic memory from minsoc_onchip_ram.v has been changed to reflect the correct model of the FPGA's onchip rams: address register and write accesses are sensitive to rising clock edge.

Documentation updated to reflect another trial and next steps to speed up the memory access from 2 clocks to 1. The negated clock approach is not standard. The right way to do it would be to use the wishbone signals cti and bte and change the minsoc_onchip_ram_top.v.		 rfajardo 5529d 11h /minsoc/branches/verilator/doc/
5 vpi path corrected in how to. rfajardo 5535d 10h /minsoc/branches/verilator/doc/
4 minsoc_bench.v had a big memory declaration to load the firmware, which was not necessary.

jp-io-vpi.vpi has to be compiled for different systems so removed from the project. Documentation now explains how to do it.

Documentation now includes:
-vpi module compilation
-gdb patch for adv_jtag_bridge
-ideas for future work on minsoc (To Do v.2)		 rfajardo 5535d 10h /minsoc/branches/verilator/doc/
3 Changed documentation
-advice to compile sw/utils before compiling target software		 rfajardo 5539d 09h /minsoc/branches/verilator/doc/
2 First commit of project. Beta status:
-testbench: working
-firmware: working
-RTL: Working for: Xilinx Spartan-3A DSP Development Kit		 rfajardo 5539d 09h /minsoc/branches/verilator/doc/

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