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Rev Log message Author Age Path
109 Creating a branche for release candidate 1.0. rfajardo 4593d 09h /minsoc/branches/verilator/prj/
108 Scripts updates to correct paths when working under Windows. Now, ModelSim, Xilinx and Altera synthesis are working on Windows through batch files.

Icarus Verilog and Altera synthesis are working as well. Job done!		 rfajardo 4593d 12h /minsoc/branches/verilator/prj/
107 Adding setup batch script for Altera synthesis on Windows.

prj/scripts/altprj.sh has now to check if it is run from cygwin in order to re-formulate the path to windows system.

Maybe the other scripts have to be updated too. This will be checked soon.		 rfajardo 4593d 15h /minsoc/branches/verilator/prj/
104 Enabling modelsim simulation for current project definition.
vhdl and verilog projects have to be separated:
-prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS.
-Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently.
-prj/scripts/simprj.sh splitted in:
-simvhdl.sh
-simverilog.sh
(they generate the input files in the right format for simulation tools)		 rfajardo 4600d 18h /minsoc/branches/verilator/prj/
97 As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. rfajardo 4637d 20h /minsoc/branches/verilator/prj/
96 Some files needed for Altera synthesis javieralso 4638d 07h /minsoc/branches/verilator/prj/
95 Makefile for Altera FPGAs fixed javieralso 4639d 10h /minsoc/branches/verilator/prj/
94 Fix bug in minsoc_top.prj for Altera synthesis javieralso 4641d 18h /minsoc/branches/verilator/prj/
93 Support for Altera synthesis. It needs some tune, but it works fine javieralso 4641d 21h /minsoc/branches/verilator/prj/
91 prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. rfajardo 4642d 20h /minsoc/branches/verilator/prj/
90 After minsoc_top.prj update, make regenerated src and xst files. rfajardo 4643d 11h /minsoc/branches/verilator/prj/
89 minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had directory entries of bench, they are gone now. rfajardo 4643d 12h /minsoc/branches/verilator/prj/
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 4643d 12h /minsoc/branches/verilator/prj/
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 4643d 13h /minsoc/branches/verilator/prj/

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