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[/] [minsoc/] [branches/] [verilator/] [prj/] [scripts/] - Rev 139

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Rev Log message Author Age Path
139 Creating a verilator branche. rfajardo 4783d 16h /minsoc/branches/verilator/prj/scripts/
110 Fixing several minor issues with the system:
-minsoc-install splitted into installation and configuration
-minsoc-configure.sh can be used to configure a fresh checked out system
-configure script used by both minsoc-configure.sh and minsoc-install.sh to configure

-rtl/verilog: svn externals fixed
-or1200 rolled back to release-1.0

-prj/scripts:
-Makefile has been used by simulation to differentiate project definition of vhdl and verilog files
-Altera was differentiating it in script
-now there are two scripts, one for vhdl and another for verilog. The differentiation occurs in Makefile as for simulation.
-altera_3c25_board/configure scripts had to be updated, vprj and vhdprj file extensions used to differentiate Verilog and VHDL project files.

-prj/src: or1200_top.prj downdated to definition of or1200_v1		 rfajardo 4810d 05h /minsoc/branches/verilator/prj/scripts/
109 Creating a branche for release candidate 1.0. rfajardo 4810d 06h /minsoc/branches/verilator/prj/scripts/
108 Scripts updates to correct paths when working under Windows. Now, ModelSim, Xilinx and Altera synthesis are working on Windows through batch files.

Icarus Verilog and Altera synthesis are working as well. Job done!		 rfajardo 4810d 10h /minsoc/branches/verilator/prj/scripts/
107 Adding setup batch script for Altera synthesis on Windows.

prj/scripts/altprj.sh has now to check if it is run from cygwin in order to re-formulate the path to windows system.

Maybe the other scripts have to be updated too. This will be checked soon.		 rfajardo 4810d 13h /minsoc/branches/verilator/prj/scripts/
104 Enabling modelsim simulation for current project definition.
vhdl and verilog projects have to be separated:
-prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS.
-Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently.
-prj/scripts/simprj.sh splitted in:
-simvhdl.sh
-simverilog.sh
(they generate the input files in the right format for simulation tools)		 rfajardo 4817d 16h /minsoc/branches/verilator/prj/scripts/
96 Some files needed for Altera synthesis javieralso 4855d 04h /minsoc/branches/verilator/prj/scripts/
91 prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. rfajardo 4859d 18h /minsoc/branches/verilator/prj/scripts/
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 4860d 09h /minsoc/branches/verilator/prj/scripts/
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 4860d 11h /minsoc/branches/verilator/prj/scripts/

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