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[/] [minsoc/] [branches/] [verilator/] [prj/] [src/] - Rev 139

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Rev Log message Author Age Path
139 Creating a verilator branche. rfajardo 4783d 15h /minsoc/branches/verilator/prj/src/
133 Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock again.

Applying Rubén Diez patch to avoid warnings on firmware load for simulation.		 rfajardo 4798d 16h /minsoc/branches/verilator/prj/src/
131 Renaming testbench modules. Adding to ifdefs without which the testbench generation can fail. rfajardo 4802d 11h /minsoc/branches/verilator/prj/src/
128 Outsourcing clocks and reset generations from minsoc_bench.v to minsoc_bench_clock.v. rfajardo 4803d 02h /minsoc/branches/verilator/prj/src/
120 ethmac.prj: a file was missing rfajardo 4809d 09h /minsoc/branches/verilator/prj/src/
113 minsoc-install.sh & minsoc-configure.sh:
-aware of location of configure.sh script
configure.sh:
-does not block on patch error

spartan3e_starter_kit & spartan3e_starter_kit_eth:
-or1200_defines.v updated

prj:
-src/blackboxes/or1200_top.v adjusted to or1200_rel1
-Makefile had a typo regarding altera vhdl files		 rfajardo 4809d 12h /minsoc/branches/verilator/prj/src/
110 Fixing several minor issues with the system:
-minsoc-install splitted into installation and configuration
-minsoc-configure.sh can be used to configure a fresh checked out system
-configure script used by both minsoc-configure.sh and minsoc-install.sh to configure

-rtl/verilog: svn externals fixed
-or1200 rolled back to release-1.0

-prj/scripts:
-Makefile has been used by simulation to differentiate project definition of vhdl and verilog files
-Altera was differentiating it in script
-now there are two scripts, one for vhdl and another for verilog. The differentiation occurs in Makefile as for simulation.
-altera_3c25_board/configure scripts had to be updated, vprj and vhdprj file extensions used to differentiate Verilog and VHDL project files.

-prj/src: or1200_top.prj downdated to definition of or1200_v1		 rfajardo 4810d 04h /minsoc/branches/verilator/prj/src/
109 Creating a branche for release candidate 1.0. rfajardo 4810d 05h /minsoc/branches/verilator/prj/src/
96 Some files needed for Altera synthesis javieralso 4855d 03h /minsoc/branches/verilator/prj/src/
89 minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had directory entries of bench, they are gone now. rfajardo 4860d 08h /minsoc/branches/verilator/prj/src/
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 4860d 08h /minsoc/branches/verilator/prj/src/
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 4860d 10h /minsoc/branches/verilator/prj/src/

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