URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [verilator/] [sw/] [utils/] - Rev 139

Rev	Log message	Author	Age	Path
139	Creating a verilator branche.	rfajardo	4783d 08h	/minsoc/branches/verilator/sw/utils/
133	Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock again. Applying Rubén Diez patch to avoid warnings on firmware load for simulation.	rfajardo	4798d 09h	/minsoc/branches/verilator/sw/utils/
109	Creating a branche for release candidate 1.0.	rfajardo	4809d 23h	/minsoc/branches/verilator/sw/utils/
37	README.txt added, describing the installation and set-up processes. Also describing to use the FAQ or forum when you have problems and finally to read minsoc.pdf (the documentation) to understand the system after everything works, to know what to do next. Clean-up of sw/utils, removing unused sources and files. Update of sw/drivers/eth.c, direct casting to avoid compile warnings. FAQ extended and with more links to the threads giving the solutions. Synthesis examples inform that the firmware tweak for Spartan3E Starter Kit using Ethernet only works for system version up to 35. minsoc.pdf and webpage now uses FPGA generic and specific codes instead of FPGA independent and dependent codes, because it suits it better.	rfajardo	5171d 06h	/minsoc/branches/verilator/sw/utils/
2	First commit of project. Beta status: -testbench: working -firmware: working -RTL: Working for: Xilinx Spartan-3A DSP Development Kit	rfajardo	5578d 07h	/minsoc/branches/verilator/sw/utils/