URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [tags/] [release-1.0/] [prj/] - Rev 95

Rev	Log message	Author	Age	Path
95	Makefile for Altera FPGAs fixed	javieralso	4670d 22h	/minsoc/tags/release-1.0/prj/
94	Fix bug in minsoc_top.prj for Altera synthesis	javieralso	4673d 06h	/minsoc/tags/release-1.0/prj/
93	Support for Altera synthesis. It needs some tune, but it works fine	javieralso	4673d 09h	/minsoc/tags/release-1.0/prj/
91	prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found.	rfajardo	4674d 08h	/minsoc/tags/release-1.0/prj/
90	After minsoc_top.prj update, make regenerated src and xst files.	rfajardo	4674d 23h	/minsoc/tags/release-1.0/prj/
89	minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had directory entries of bench, they are gone now.	rfajardo	4675d 00h	/minsoc/tags/release-1.0/prj/
88	Project structure, Xilinx Makefiles and simulation working.	rfajardo	4675d 00h	/minsoc/tags/release-1.0/prj/
85	Central project definition under prj. Synthesis and simulation take their project files from here.	rfajardo	4675d 01h	/minsoc/tags/release-1.0/prj/