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[/] [minsoc/] [trunk/] [sim/] - Rev 66

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Rev	Log message	Author	Age	Path
64	firmware makefiles: -every firmware makefile has now complete dependency. This also includes dependency on files under minsoc/backend (target specific files). That means, that if some target specific header changes, the support library dependent on it will be compiled. That will always happen, even if you compile the uart firmware. In other words, if you want to use uart firmware, you can always simply compile uart by issuing make all. If anything has changed, backend files, support library, drivers, it will update everything for you. -TODO: dependency can be automatic created by using make together with gcc. Use it instead of declaring all dependencies manually. Makefile system for synthesis: -the dependency for every implementation step has been checked and is working fine. -Makefile plus support files have been moved to minsoc/syn/src -make usage is still under syn through files generated by backend bashscripts Backend: -files under backend are target specific files used for the system to work -firmware compilation -system simulation -system implementation -This directory is populated by visiting one of its subdirectories and typing ./configure backend/spartan3a_dsp_kit: -working on FPGA backend/spartan3e_starter_kit: -has to be tested backend/ml509: -missing files have to be copied and adapted, configure script has to be copied and adapted backend/std: -include files necessary for firmware compilation and system configuration -it does not include files for synthesis and is not synthesizable	rfajardo	4939d 06h	/minsoc/trunk/sim/
60	Selection of memory model or implementation memory is now made on minsoc_bench_defines.v. It is done by a definition instead of including different files for simulation. minsoc_bench_defines.v definition of reset level was not correct. It based the level decision on defineds POSITIVE_RESET or NEGATIVE_RESET, which couldn't be defined by then, since minsoc_defines.v is not included in minsoc_bench_defines.v. The decision has been moved to minsoc_bench.v and made a localparam instead of a definition.	rfajardo	4943d 18h	/minsoc/trunk/sim/
34	start_server changed: '-t' option of adv_jtag_bridge for vpi connection on simulation removed. or1200_v3 will not pass on CPU self test. FAQ completed with asked questions since Februrary 2010. INSTALL informs bsdl files only have to be copied to home directory for Xilinx devices. synthesis_examples title includes Minimal OpenRISC System on Chip.	rfajardo	5139d 02h	/minsoc/trunk/sim/
31	Adaption to or1200_r3. It is still important to change or1200_defines.v: -`define OR1200_BOOT_ADR 32'hf0000100 to `define OR1200_BOOT_ADR 32'h00000100	rfajardo	5216d 08h	/minsoc/trunk/sim/
30	minsoc SoC documentation had 2 small typo corrections. Performance penalty due to addition of register addresses was a wrong assumption. On project description "is composed by" -> "consists of". Thanks to Wojciech A. Koszek. howto, at some places the howto did not tell the path from the files being talked about. I tried to always specify the path for every commented file. Scripts for running the simulation called bash instead of sh. For compatibility reasons sh is now used, this should affect noone. Scripts do not use bash specific commands and generally every UNIX like computer has sh. Thanks again to Wojciech A. Koszek, who adapted that to port it to FreeBSD.	rfajardo	5259d 07h	/minsoc/trunk/sim/
18	Deprecated comments removed from the file listing files.	rfajardo	5469d 07h	/minsoc/trunk/sim/
17	Ethernet testbench speed penalty solved. Now Ethernet of testbench and minsoc can be enabled by only uncommenting `define ETHERNET on minsoc_defines.v. send_mac, get_mac and uart_send tasks have been included/improved. Also a testbench, which works for both included firmwares is added. (eth and uart) If ETHERNET is defined for the SoC, both firmwares will complete successfully. If not, the eth firmware will stall when trying to access the Ethernet module.	rfajardo	5471d 02h	/minsoc/trunk/sim/
10	Added a file containing models for each FPGA memory instances used in or1200. The file is in bench/verilog/sim_lib/fpga_memory_primitives.v. With it, people who change the or1200_defines.v inside of the project structure will still be able to simulate, using house-made models, not from manufacturers. minsoc_bench.v had to be extended by the task, init_fpga_memory, to initialize the dual or two port memories instances of or1200. This has to be done based on the type of memory used, so many different instantiations based on definitions. Somehow or1200 expects all memory values to be 0 upon start, so this is necessary.	rfajardo	5510d 01h	/minsoc/trunk/sim/
2	First commit of project. Beta status: -testbench: working -firmware: working -RTL: Working for: Xilinx Spartan-3A DSP Development Kit	rfajardo	5531d 05h	/minsoc/trunk/sim/

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