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Rev	Log message	Author	Age	Path
60	Selection of memory model or implementation memory is now made on minsoc_bench_defines.v. It is done by a definition instead of including different files for simulation. minsoc_bench_defines.v definition of reset level was not correct. It based the level decision on defineds POSITIVE_RESET or NEGATIVE_RESET, which couldn't be defined by then, since minsoc_defines.v is not included in minsoc_bench_defines.v. The decision has been moved to minsoc_bench.v and made a localparam instead of a definition.	rfajardo	4938d 00h	/minsoc/trunk/sim/run/
34	start_server changed: '-t' option of adv_jtag_bridge for vpi connection on simulation removed. or1200_v3 will not pass on CPU self test. FAQ completed with asked questions since Februrary 2010. INSTALL informs bsdl files only have to be copied to home directory for Xilinx devices. synthesis_examples title includes Minimal OpenRISC System on Chip.	rfajardo	5133d 08h	/minsoc/trunk/sim/run/
30	minsoc SoC documentation had 2 small typo corrections. Performance penalty due to addition of register addresses was a wrong assumption. On project description "is composed by" -> "consists of". Thanks to Wojciech A. Koszek. howto, at some places the howto did not tell the path from the files being talked about. I tried to always specify the path for every commented file. Scripts for running the simulation called bash instead of sh. For compatibility reasons sh is now used, this should affect noone. Scripts do not use bash specific commands and generally every UNIX like computer has sh. Thanks again to Wojciech A. Koszek, who adapted that to port it to FreeBSD.	rfajardo	5253d 12h	/minsoc/trunk/sim/run/
17	Ethernet testbench speed penalty solved. Now Ethernet of testbench and minsoc can be enabled by only uncommenting `define ETHERNET on minsoc_defines.v. send_mac, get_mac and uart_send tasks have been included/improved. Also a testbench, which works for both included firmwares is added. (eth and uart) If ETHERNET is defined for the SoC, both firmwares will complete successfully. If not, the eth firmware will stall when trying to access the Ethernet module.	rfajardo	5465d 08h	/minsoc/trunk/sim/run/
2	First commit of project. Beta status: -testbench: working -firmware: working -RTL: Working for: Xilinx Spartan-3A DSP Development Kit	rfajardo	5525d 11h	/minsoc/trunk/sim/run/

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