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[/] [minsoc/] [trunk/] [sw/] [uart/] - Rev 158

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Rev	Log message	Author	Age	Path
158	Adding de2_115_board port, thanks to Richard Hasha. Support to JSP (JTAG Serial Port) working well. Also provided by Richard Hasha. Different interconnect configurations per board are not straightforward on MinSoC. New added modules or definitions for addresses have to be carried over to other boards. Furthermore, extra modules can be shared among all projects. Thus, it is better to have this centralized: -Removing interconnect configuration from minsoc_defines.v. There is an interconnect_defines.v file on rtl/verilog. The software counterpart is interconnect.h on sw/drivers. Including a jsp firmware. It is basically the uart firmware but using JSP instead. Added to all board configure scripts to be compiled on configuration. prj/srcs extended to include jsp and interconnec_defines.v. spartan3e_starter_kit_eth lost UART (does not fit) and uses JSP instead now.	rfajardo	4686d 04h	/minsoc/trunk/sw/uart/
149	Merging differences of release candidate 1.0 revision 140:148 with trunk.	rfajardo	4724d 14h	/minsoc/trunk/sw/uart/
80	Establishing a better Makefile system for firmwares.	rfajardo	4825d 13h	/minsoc/trunk/sw/uart/
65	Files missing in the last commit. backend/std/configure sw: eth, uart and driver Makefiles	rfajardo	4933d 11h	/minsoc/trunk/sw/uart/
64	firmware makefiles: -every firmware makefile has now complete dependency. This also includes dependency on files under minsoc/backend (target specific files). That means, that if some target specific header changes, the support library dependent on it will be compiled. That will always happen, even if you compile the uart firmware. In other words, if you want to use uart firmware, you can always simply compile uart by issuing make all. If anything has changed, backend files, support library, drivers, it will update everything for you. -TODO: dependency can be automatic created by using make together with gcc. Use it instead of declaring all dependencies manually. Makefile system for synthesis: -the dependency for every implementation step has been checked and is working fine. -Makefile plus support files have been moved to minsoc/syn/src -make usage is still under syn through files generated by backend bashscripts Backend: -files under backend are target specific files used for the system to work -firmware compilation -system simulation -system implementation -This directory is populated by visiting one of its subdirectories and typing ./configure backend/spartan3a_dsp_kit: -working on FPGA backend/spartan3e_starter_kit: -has to be tested backend/ml509: -missing files have to be copied and adapted, configure script has to be copied and adapted backend/std: -include files necessary for firmware compilation and system configuration -it does not include files for synthesis and is not synthesizable	rfajardo	4933d 13h	/minsoc/trunk/sw/uart/
55	Adjusting Makefiles to compile correctly with new firmware updates. 1) except.o not included into libsupport.a. 2) libsupport.a linked to except.o, now in correct order: ld libsupport.a except.o -o executable (not the other way around) 3) int.c was not being compiled because of a #ifdef which is not set anywhere	rfajardo	4946d 10h	/minsoc/trunk/sw/uart/
53	Indentation, deleting redundant files and adding externals	ConX.	4946d 13h	/minsoc/trunk/sw/uart/
39	FAQ: -Adv_jtag_bridge self test fails? -included now SoC flow mistakes -forgetting to upload the bitfile -leaving clock unconnected -older information is now under "Known Issues" right below of SoC flow mistakes Software: -eth: included eth.h is from drivers and not from this directory. eth.h from this directory is old and has been removed. -uart: included uart.h is from drivers and not from this directory. uart.h from this directory is old and has been removed.	rfajardo	5053d 01h	/minsoc/trunk/sw/uart/
38	Small update to HOWTO: advices now to also include the ucf (pinout) file, for forgetful people :-). FAQ: Added another option (hint) as a solution for people with on-board Xilinx USB cables, which do not reset. uart.c: now uses the IRQ line definition instead of the line number directly.	rfajardo	5088d 00h	/minsoc/trunk/sw/uart/
36	utils: -adding a 32 to 8 bit Wishbone bridge to connect 8 bit modules to the MinSoC interconnect. -adding a Linux driver for parallel cables for the adv_jtag_bridge. It circumvents the necessity of privilege to run adv_jtag_bridge with cables xpc3 and xess. sw/support: support library has been made completely standalone. That means, it is now independent from uClib and/or newlib. Thanks to Wojciech A. Koszek for his contribution on this. sw/drivers: a driver library has been included, which supply drivers for the OpenRISC timer; and for UART, Ethernet, I2C, and CAN modules from OpenCores. sw/uart and sw/eth: they don't provide code to control the UART and Ethernet controllers anymore. They use the drivers library instead. Documentation: -FAQ extended: -table of contents -explanation of how to use the 32 to 8 bit Wishbone bridge -how to make adv_jtag_bridge work without privilege requirement for xess or xpc3 -explanation of locking problem of xpc_usb cable -explanation of what to do if the cable is built on-board -INSTALL: -patching of gdb only required if version is 6.8, explanation on FAQ now. -HOWTO: -instruct to compile drivers library -remove line numbers information on what to edit, better leave it to be found only by the informed context. -adv_jtag_bridge execution now without 'sudo'. Note included that 'sudo' is required for Linux and xess or xpc3. Reference to FAQ to avoid this requirement.	rfajardo	5119d 07h	/minsoc/trunk/sw/uart/
2	First commit of project. Beta status: -testbench: working -firmware: working -RTL: Working for: Xilinx Spartan-3A DSP Development Kit	rfajardo	5525d 12h	/minsoc/trunk/sw/uart/

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