URL https://opencores.org/ocsvn/mips32r1/mips32r1/trunk

Subversion Repositories mips32r1

[/] [mips32r1/] - Rev 13

Rev	Log message	Author	Age	Path
13	The project has moved to GitHub.	ayersg	3811d 11h	/mips32r1/
12	Updated SoC bit file with hardware divider. Changed SoC frequency to a more conservative 33/66MHz clock. SoC BRAM cores must now be generated by the user. Added a README to the standalone processor directory.	ayersg	4220d 11h	/mips32r1/
11	SoC project files updated to include divide module.	ayersg	4227d 17h	/mips32r1/
10	Added hardware divide support. Thanks to Neil Russell for contributing the divide module.	ayersg	4227d 18h	/mips32r1/
9	Minor code cleanup, changed default BE bit in CP0.	ayersg	4227d 18h	/mips32r1/
8	Added information for regenerating the BRAM core for the SoC.	ayersg	4237d 12h	/mips32r1/
7	Corrected functionality of Jal.	ayersg	4237d 13h	/mips32r1/
6		ayersg	4251d 11h	/mips32r1/
5	Added a howto for getting started.	ayersg	4252d 15h	/mips32r1/
4	Added a howto for getting started.	ayersg	4252d 15h	/mips32r1/
3	Made whitespace consistent in all Verilog files.	ayersg	4254d 18h	/mips32r1/
2	Initial release	ayersg	4255d 05h	/mips32r1/
1	The project and the structure was created	root	4256d 05h	/mips32r1/