URL https://opencores.org/ocsvn/mips32r1/mips32r1/trunk

Subversion Repositories mips32r1

[/] [mips32r1/] - Rev 11

Rev	Log message	Author	Age	Path
11	SoC project files updated to include divide module.	ayersg	4230d 08h	/mips32r1/
10	Added hardware divide support. Thanks to Neil Russell for contributing the divide module.	ayersg	4230d 09h	/mips32r1/
9	Minor code cleanup, changed default BE bit in CP0.	ayersg	4230d 09h	/mips32r1/
8	Added information for regenerating the BRAM core for the SoC.	ayersg	4240d 03h	/mips32r1/
7	Corrected functionality of Jal.	ayersg	4240d 04h	/mips32r1/
6		ayersg	4254d 02h	/mips32r1/
5	Added a howto for getting started.	ayersg	4255d 06h	/mips32r1/
4	Added a howto for getting started.	ayersg	4255d 06h	/mips32r1/
3	Made whitespace consistent in all Verilog files.	ayersg	4257d 09h	/mips32r1/
2	Initial release	ayersg	4257d 20h	/mips32r1/
1	The project and the structure was created	root	4258d 20h	/mips32r1/