URL https://opencores.org/ocsvn/mips32r1/mips32r1/trunk

Subversion Repositories mips32r1

[/] [mips32r1/] [trunk/] [Hardware/] [XUPV5-LX110T_SoC/] [MIPS32-Pipelined-Hw/] [src/] - Rev 12

Rev	Log message	Author	Age	Path
12	Updated SoC bit file with hardware divider. Changed SoC frequency to a more conservative 33/66MHz clock. SoC BRAM cores must now be generated by the user. Added a README to the standalone processor directory.	ayersg	4213d 20h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/
11	SoC project files updated to include divide module.	ayersg	4221d 02h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/
10	Added hardware divide support. Thanks to Neil Russell for contributing the divide module.	ayersg	4221d 03h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/
9	Minor code cleanup, changed default BE bit in CP0.	ayersg	4221d 03h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/
7	Corrected functionality of Jal.	ayersg	4230d 22h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/
3	Made whitespace consistent in all Verilog files.	ayersg	4248d 03h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/
2	Initial release	ayersg	4248d 14h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/