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[/] [mkjpeg/] [trunk/] [design/] - Rev 63

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Rev Log message Author Age Path
63 Added YUV input support. mikel262 5257d 02h /mkjpeg/trunk/design/
61 Design now uses 4:2:2 chroma subsampling mikel262 5298d 15h /mkjpeg/trunk/design/
58 fix for C_EXTRA_LINES=0 mikel262 5301d 06h /mkjpeg/trunk/design/
57 default max performance mikel262 5301d 16h /mkjpeg/trunk/design/
56 BUF_FIFO redesign, for memory/performance tradeoff mikel262 5301d 17h /mkjpeg/trunk/design/
52 Redesigned BUF_FIFO.vhd to significantly reduce area utilization.
Only memory optimized version now possible.		 mikel262 5312d 18h /mkjpeg/trunk/design/
51 fix in buf fifo (synthesis problem) mikel262 5316d 16h /mkjpeg/trunk/design/
50 mikel262 5317d 02h /mkjpeg/trunk/design/
49 Added 16 bit RGB 565 input format. mikel262 5317d 02h /mkjpeg/trunk/design/
46 x1 mikel262 5326d 04h /mkjpeg/trunk/design/
44 stall re-added mikel262 5326d 04h /mkjpeg/trunk/design/
43 stall readded mikel262 5326d 04h /mkjpeg/trunk/design/
42 Added backpressure/stallability of output interface. mikel262 5329d 16h /mkjpeg/trunk/design/
41 Fixed RLE ZRL bug occurring at end of 8x8 block mikel262 5467d 04h /mkjpeg/trunk/design/
40 Fixed few bugs in BUF_FIFO and RLE encoder. mikel262 5509d 18h /mkjpeg/trunk/design/
39 bug fix. mikel262 5512d 17h /mkjpeg/trunk/design/
38 Reduced processing latency of Huffman encoding mikel262 5537d 17h /mkjpeg/trunk/design/
37 Replaced VHDL Header RAM with Verilog, initialized via readmemh from hex file. mikel262 5541d 21h /mkjpeg/trunk/design/
36 Fixed RLE ZRL bug. Added Chrominance Huffman tables. Fixed num encoded bytes bug. mikel262 5543d 17h /mkjpeg/trunk/design/
34 Moved Quantizer to separate pipeline stage to balance processing chain load. mikel262 5544d 13h /mkjpeg/trunk/design/

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