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Rev Log message Author Age Path
124 Holger Lohn's fix for interrupts when 3-state pipeline enabled. rhoads 7429d 07h /mlite/trunk/
123 Uncomment out the Altera portion. Xilinx users may need to re-comment out this section. rhoads 7496d 08h /mlite/trunk/
122 Added comment to explain why c_bus isn't delayed but reg_dest is delayed. rhoads 7560d 08h /mlite/trunk/
121 Added Matthias Gruenewald's tri-state area-optimized option rhoads 7571d 20h /mlite/trunk/
120 Make generics "GENERIC" rhoads 7571d 20h /mlite/trunk/
119 Opcodes from count.c rhoads 7610d 07h /mlite/trunk/
118 Merged Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7610d 07h /mlite/trunk/
117 Part of Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7610d 07h /mlite/trunk/
116 Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7610d 08h /mlite/trunk/
115 Matthias Grunewald's changes for Xilinx FPGA dual-port RAM. rhoads 7610d 08h /mlite/trunk/
114 Matthias Grunewald's changes to get synthesis to work with Synopsys' FPGA Compiler II. rhoads 7610d 08h /mlite/trunk/
113 Matthias Grunewald's bug fixes:
Branch and compare instructions didn't interpret immediate as signed.		 rhoads 7610d 08h /mlite/trunk/
112 Merged Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7610d 08h /mlite/trunk/
111 Updated to work with new convert.exe which updates opcodes to set $4, $5, and $sp. rhoads 7610d 08h /mlite/trunk/
110 support > 64kb memory with bss_start, bss_end, sp rhoads 7884d 04h /mlite/trunk/
109 support > 64kb memory with bss_start, bss_end, and sp rhoads 7884d 04h /mlite/trunk/
108 changed interrupt vector from 0x30 to 0x3c rhoads 7884d 04h /mlite/trunk/
107 merged rising_edge(clk) statements rhoads 7884d 04h /mlite/trunk/
106 better test mem_pause rhoads 7887d 06h /mlite/trunk/
105 better test mem_pause rhoads 7887d 07h /mlite/trunk/

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