URL https://opencores.org/ocsvn/mlite/mlite/trunk

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[/] [mlite/] [trunk/] [vhdl/] - Rev 350

Rev	Log message	Author	Age	Path
350		root	5597d 19h	/mlite/trunk/vhdl/
348	Added comment for 32MB and 128MB DDR parts	rhoads	5628d 14h	/trunk/vhdl/
347	Xilinx ISE Project file	rhoads	5628d 14h	/trunk/vhdl/
346	Support optional 4KB cache	rhoads	5665d 14h	/trunk/vhdl/
345	Commented out optional mult speedup	rhoads	5669d 10h	/trunk/vhdl/
344	Fixed compiler warning	rhoads	5669d 11h	/trunk/vhdl/
343	Initial working cache	rhoads	5669d 11h	/trunk/vhdl/
337	Initial attempt at a cache	rhoads	5674d 15h	/trunk/vhdl/
335	Use enable signal for byte_we	rhoads	5716d 09h	/trunk/vhdl/
334	Short time for averaging read signal for 12.5 MHz case	rhoads	5726d 09h	/trunk/vhdl/
333	Updated Altera lpm_ram_dp usage for Cyclone FPGAs	rhoads	5726d 09h	/trunk/vhdl/
332	Updated Altera lpm_ram_dp	rhoads	5726d 09h	/trunk/vhdl/
331	Commented out unconnected signals	rhoads	5787d 09h	/trunk/vhdl/
329	Fix interrupt line comment	rhoads	5878d 07h	/trunk/vhdl/
288	Added Ethernet MAC with DMA	rhoads	6005d 07h	/trunk/vhdl/
287	Added ethernet and flash control	rhoads	6005d 07h	/trunk/vhdl/
286	Added eth_dma	rhoads	6005d 07h	/trunk/vhdl/
285	Added eth_dma	rhoads	6005d 09h	/trunk/vhdl/
284	Removed unsupported branch likely opcodes	rhoads	6005d 09h	/trunk/vhdl/
280	Fix comment	rhoads	6022d 07h	/trunk/vhdl/