URL https://opencores.org/ocsvn/mlite/mlite/trunk

Subversion Repositories mlite

[/] [mlite/] [trunk/] [vhdl/] - Rev 112

Rev	Log message	Author	Age	Path
112	Merged Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA.	rhoads	7506d 11h	/mlite/trunk/vhdl/
108	changed interrupt vector from 0x30 to 0x3c	rhoads	7780d 07h	/mlite/trunk/vhdl/
107	merged rising_edge(clk) statements	rhoads	7780d 07h	/mlite/trunk/vhdl/
106	better test mem_pause	rhoads	7783d 09h	/mlite/trunk/vhdl/
105	better test mem_pause	rhoads	7783d 10h	/mlite/trunk/vhdl/
103	shorten similation times	rhoads	7784d 09h	/mlite/trunk/vhdl/
102	permit testing mem_pause	rhoads	7784d 09h	/mlite/trunk/vhdl/
101	Correctly freeze the pipeline when mem_pause = '1'	rhoads	7784d 09h	/mlite/trunk/vhdl/
99	correct upper 32-bits for mult(-1,-1)	rhoads	7926d 08h	/mlite/trunk/vhdl/
98	Fix size of GENERIC ram.	rhoads	7931d 07h	/mlite/trunk/vhdl/
97	added documentation	rhoads	7995d 12h	/mlite/trunk/vhdl/
96	Simplify take_branch	rhoads	8029d 14h	/mlite/trunk/vhdl/
95	register mem_write and mem_byte_sel for speed calculations	rhoads	8029d 14h	/mlite/trunk/vhdl/
93	make run now runs for 500 us	rhoads	8031d 08h	/mlite/trunk/vhdl/
92	Updated	rhoads	8031d 08h	/mlite/trunk/vhdl/
91	Removed unused alu_function_type entries	rhoads	8031d 08h	/mlite/trunk/vhdl/
90	Now multiplies two bits at a time	rhoads	8031d 08h	/mlite/trunk/vhdl/
89	Use address_reg instead of address_data to break timing slow down	rhoads	8031d 08h	/mlite/trunk/vhdl/
88	Cleanup spaces	rhoads	8031d 08h	/mlite/trunk/vhdl/
87	Seperated left and right shift variables	rhoads	8031d 08h	/mlite/trunk/vhdl/