URL https://opencores.org/ocsvn/mlite/mlite/trunk

Subversion Repositories mlite

[/] [mlite/] [trunk/] [vhdl/] - Rev 114

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
114	Matthias Grunewald's changes to get synthesis to work with Synopsys' FPGA Compiler II.	rhoads	7519d 04h	/mlite/trunk/vhdl/
113	Matthias Grunewald's bug fixes: Branch and compare instructions didn't interpret immediate as signed.	rhoads	7519d 04h	/mlite/trunk/vhdl/
112	Merged Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA.	rhoads	7519d 04h	/mlite/trunk/vhdl/
108	changed interrupt vector from 0x30 to 0x3c	rhoads	7793d 01h	/mlite/trunk/vhdl/
107	merged rising_edge(clk) statements	rhoads	7793d 01h	/mlite/trunk/vhdl/
106	better test mem_pause	rhoads	7796d 03h	/mlite/trunk/vhdl/
105	better test mem_pause	rhoads	7796d 03h	/mlite/trunk/vhdl/
103	shorten similation times	rhoads	7797d 02h	/mlite/trunk/vhdl/
102	permit testing mem_pause	rhoads	7797d 02h	/mlite/trunk/vhdl/
101	Correctly freeze the pipeline when mem_pause = '1'	rhoads	7797d 02h	/mlite/trunk/vhdl/
99	correct upper 32-bits for mult(-1,-1)	rhoads	7939d 02h	/mlite/trunk/vhdl/
98	Fix size of GENERIC ram.	rhoads	7944d 00h	/mlite/trunk/vhdl/
97	added documentation	rhoads	8008d 06h	/mlite/trunk/vhdl/
96	Simplify take_branch	rhoads	8042d 08h	/mlite/trunk/vhdl/
95	register mem_write and mem_byte_sel for speed calculations	rhoads	8042d 08h	/mlite/trunk/vhdl/
93	make run now runs for 500 us	rhoads	8044d 01h	/mlite/trunk/vhdl/
92	Updated	rhoads	8044d 01h	/mlite/trunk/vhdl/
91	Removed unused alu_function_type entries	rhoads	8044d 01h	/mlite/trunk/vhdl/
90	Now multiplies two bits at a time	rhoads	8044d 01h	/mlite/trunk/vhdl/
89	Use address_reg instead of address_data to break timing slow down	rhoads	8044d 01h	/mlite/trunk/vhdl/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories mlite

[/] [mlite/] [trunk/] [vhdl/] - Rev 114

Filtering Options